Presentation

on
“Analysis and Design of Phase Frequency Detector(PFD)-Charge
Pump for High Speed PLL in CMOS technology”
Under the guidance of
Supervisor: Co-Supervisor:
Dr. Syed Hasan Saeed Dr. Deepak Balodi
Professor and Head, Associate Professor
Department of ECE, Department of ECE,
Integral University, Lucknow BBDEC, Lucknow
Presented By:
Mohammad Amir Ansari
Enrolment No. :1901118
 Content
 Introduction
 Last RDC Comment
 Literature review
 Research Gap
 Research Objectives
 Methodology
 Work Progress
 References

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 Introduction to PFD and Charge-Pump

Figure : Phase Frequency Detector conceptual block diagram

 The output signals of the PFD are fed to the charge pump.
 The output voltage of the charge pump controls the output frequency of the
VCO, so with a change happens at the input of the CP the output voltage will
change which will change the output frequency of the VCO.

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 Introduction to PFD and Charge-Pump Cont…
 The phase frequency detector (PFD) compares the phase and frequency of
the two clocks and produces either a pump-up or pump-down signal depending
on whether the phase of the on-chip clock is lagging or leading the external
reference clock.

 The charge pump increases the voltage on the loop filter capacitor when given a
pump-up signal and decreases this voltage when given a pump-down signal.

 The loop filter is a low- pass filter used to average out the high-frequency
components of the charge pump output and set the bandwidth of the PLL
feedback loop.

 The VCO produces an output clock the frequency of which is proportional

to its input voltage.

 The frequency divider divides down the frequency of the VCO output clock to
produce a clock signal with a frequency in the same range as that of the
reference clock.

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 Challenges with PLL and PFD-CP design
Non-ideality in PLL: The non-idealities in PLL introduces
charge pump current mismatch,
current sharing,
switching delays and
leakage in devices

Jitter and Phase noise

PLL dynamics
 Loop bandwidth (Locking speed)
 Stability (Phase Margin)

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 Comments: Last RDC(held on 02.02.2021) 

 Recommended for Continuation

 Co-Supervisor: Dr. Deepak Balodi

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 Literature Review
Title Author Year Remark
ALow-Power and Adel Rezaeian 2020 Recently in the year 2020, A new low-power
High-Frequency et al. and high-frequency PFD with minimal reset
Phase Frequency path time is presented in this paper. Using D
Detector for a flip-flops in TSPC logic by just seven
3.33-GHz Delay transistors and an AND gate in GDI logic with
Locked Loop just two transistors led to shorter path time for
resetting the PFD and lower power dissipation
A Dead-Zone- H. Lad 2020 In the year 2020 have present a novel
Free Zero Blind- Kirankumar architecture for phase frequency detector
et al. (PFD) which eliminates the blind zone effect
Zone High-Speed as well as the dead zone for a charge-pump
Phase Frequency phase locked loop (CP-PLL). This PFD is
Detector for designed in 65 nm CMOS technology, and its
Charge-Pump functionality is verified across process, voltage
PLL and temperature variations. Achieved
maximum frequency of operation (Fmax)
which is suitable for high reference clocked
fast settling PLLs.

09-08-2021 Mohd Amir Ansari 7

 Literature Review
Low-Power Sobhan 2019 This paper has recently tried to design and
High-Frequency Sofimowloodi analyze the performance of a phase frequency
Phase Frequency et al. detector. In addition to very low dead zone, it
Detector for has low power consumption and high
Minimal Blind- frequency performance. Simulations are
Zone Phase- carried out in the technology of 0.13 µm.
Locked Loops

Phase Frequency Wu-Hsin Chen 2010 Author have presented a modified PFD that
Detector et al. significantly reduces the precharging time.
with Minimal The proposed technique allows reducing the
Blind Zone for blind zone compared with the widely adopted
Fast Frequency topology having only delay cells. Fabricated
Acquisition in a 130-nm CMOS technology, the measured
blind zone is minimal which is close to the
limit imposed by PVT variations.

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 Literature Review
A Review of Andrea Ballo 2019 In this applications, the power
Charge Pump et al. management section can be profitably
Topologies for implemented, exploiting CPs. Indeed,
the Power presently, many different CP topologies
Management of have been presented in literature. Finally,
IoT Nodes a data-driven comparison was also
provided, allowing for quantitative insight
into the state-of-the-art of integrated CPs.

Design of Low Aniruddha 2019 The planned PFD have zero dead zone.
Power, Low Kailukea et Mostly switch drain charge pump suffer
Jitter PLL for al. from channel length modulation impact
WiMAX and current mismatching particularly for
Application in short channel length CMOS process. Gain
0.18um CMOS boosting Charge pump reduces the
process outcome of channel length modulation
and current mismatching due to high
output impedance.

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 Literature Review
A Gain- Abdulqader 2019 In this paper a single-stage power
Controlled, Low- Mahmoud et management unit to boost and regulate a
Leakage Dickson al. low supply voltage for CMOS system-on-
Charge Pump for chip (SoC) applications. It consists of
Energy- low-leakage, enhanced Dickson charge
Harvesting pump (DCP) that utilizes both stage and
Applications frequency modulation (FM) techniques to
achieve high efficiency and lower area.

High-Voltage C. Arul 2019 This paper presented an enhanced

Gain CMOS Murugan et complementary metal oxide
Charge Pump at al. semiconductor(CMOS) charge pump
Sub threshold (CP) circuit with improved gain and
Operation efficiency by dynamically controlling
Regime for Low substrate and gate terminals of PMOS
Power transistor. The proposed novel charge
Applications pump provides good performance even at
low voltage.
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 Research Gap
 A further Jitter minimization is still to be achieved to the best level possible.

 Obtaining a Mixed signal design integration via combining PFD (Digital block)
with the Charge-Pump-Filter (Analog Block).

 Obtaining the low power dissipation (below 50mW) for the proposed PFD-CP
architecture in conventional CMOS process.

 Most of the proposed PFD-CP design architectures are independent in the nature
and are operationally tested in isolation, whereas the proposed design will be
tested to work in synchronism of PLL operation.

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 Research Objectives(To be approved)
 To understand the latest trends of PFD-Charge Pump challenges by literature
review. Literature Review
 To evaluate the problems associated and finalizing the design constraints of
PFD-Charge Pump.
 To design and simulation of a prototype PFD-Charge Pump using (SPICE) in
RF domain.
 To finalize the circuit design for improvised PFD-Charge pump and simulation
in ADS (RF-SPICE).
 To evaluate performance of the design and comparison against contemporary
design trends in the literatures.

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 Methodology of the Research Work

 To accomplish this research work, the circuital topology would be implemented on

RF-SPICE platform.

 Domain: AMS (Analog-Mixed Signal) Design

 Platform/Tool: SPICE (Circuit architecture and Simulation)

 Software: TANNER EDA (TSPICE/ HSPICE) or ADS

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 WORK PROGRESS
Previous accomplishments:

 Many articles/research papers were analyzed and the objectives were set to accomplish the
same.
 Successfully arrived at the problem statement with the help of literature pool towards charge
pump based PLLs and PFDs.
 Basic understanding of the software environment and prototype designs have been achieved.
 Block level behavioral model has been planned and worked upon with the mathematical
parameters (in ADS environment). The outcomes validate the benefits and objectives laid
upon.
 A prototype circuit for low power charge pump has been attempted and still is in progress.
 A review paper has been communicated to be published in a conference proceeding/journal.

 
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Plan for next six months:
  
 Few more recent articles consisting latest design issues will be considered and
incorporated.

 The block level mathematical design will be further improvised to tackle current
mismatch and power drain issues.

 The circuit level (SPICE) design and simulation will be performed for charge
pump in CMOS technology.

 A SCOPUS/SCI level paper publication will be attempted for the final design
and simulation results.

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 References
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[11] Esdras Juárez-Hernández, and Alejandro Díaz-Sánchez. “A Novel CMOS Charge-Pump
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[17] Sung Sik Park, Ju Sang Lee, Sang Dae Yu, “Phase Frequency Detector and Charge
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 THANK YOU

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