CHAPTER 2

ARITHMETIC AND LOGIC (CONT)

2.3 BUILD SEQUENTIAL LOGIC

CIRCUIT

1
2.3.1 DEFINE SEQUENTIAL LOGIC CIRCUIT
•  Sequential logic circuit is a memory property circuit
and have output that depend on the previous
output(s) and current inputs
• In general, a sequential circuit is synchronised by the
clock signal (pulse) – synchronised circuit
• The basic block diagram for a sequential circuit is
memory device called flip-flop that consist of 2 stable
operational states (outputs) Q and .

2
 COMBINATIONAL Versus
SEQUENTIAL LOGIC CIRCUIT
Combinational Logic Circuit Sequential Logic Circuit
Is a circuit which output is determined Composed of combinational circuit and
by the input have some form of inherent memory

Are made up from basic logic NAND, The current output of a sequential
NOR or NOT gates that are combined circuit depends not only on the
or connected together to produce current input, but also on the past
more complicated switching circuits. history of inputs.

Have no memory, timing or feedback The memory will save information

in binary which called state of a
sequential circuit at that time

Example : decoders, multiplexers, full Output of sequential circuit not only

and half adder based on input but also determined
by value of present state in memory
3
 COMBINATIONAL Versus
SEQUENTIAL LOGIC CIRCUIT

Combinational Logic Circuit Sequential Logic Circuit

The circuit whose output, at any The circuit whose output at any
immediate time, depends only on the immediate time depends not only on the
input present at that instant only is input present but also on the past
known as a combinational circuit. output,  is known as sequential circuit

These types of circuits have no memory These types of circuits have a memory
unit. unit to store the past output.
It is Faster. It is Slower.

Examples of combinational circuits are a Examples of sequential circuits are flip-

half adder, full adder, magnitude flop, register, counter, clocks, etc. 3
comparator, multiplexer, demultiplexer,
etc.
2.3.2 List the types of Flip Flop
You have to know below
Clocked features for each types
SR flip of flip flop :-
SR flip flop • Logic gates or
flop
circuit diagram
• Symbol
JK flip T flip diagram
• Truth table
flop flop • Timing diagram

D flip
flop

DFC10093 COMPUTER SYSTEM ARCHITECTURE 5

a) Set Reset Flip Flop ( SR FF)
•  A flip-flop circuit can be constructed from two NAND gates
or
two NOR gates.
• Each flip-flop has two outputs, Q and , and two inputs, set
and reset.
• 4 states:
– Three stable [Set, Reset, and Keep(No Change)].
– One not stable [Unused (Invalid)].
• 2 inputs, 2 outputs.
• May also contain clock (CLK) signal.

Set -> put value for Q=1

Reset - > put value for
Q=0
Keep / Hold / Unchanged
DFC10093 COMPUTER SYSTEM ARCHITECTURE 6
-> maintained the past
i) NOR GATES SR FLIP FLOP (active HIGH)

Basic flip-flop circuit with NOR

gates

LOGIC GATES
TRUTH TABLE

S Q
R

SYMBOL
TIMING DIAGRAM NOR
GATES SR FLIP-FLOP

9
TIMING DIAGRAM NOR GATES SR FLIP-FLOP

9
ii) NAND GATES SR FLIP FLOP (active LOW)
Basic flip-flop circuit with NAND
gates

LOGIC GATES
TRUTH TABLE

S Q
R

SYMBOL
TIMING DIAGRAM NAND GATES SR FLIP-FLOP

9
b)Clocked SR Flip-Flop LOGIC GATES SYMBOL

TRUTH TABLE

The clocked SR flip-flop consists of a basic NOR flip- flop and two AND gates.
The outputs of the two AND gates remain at logic ‘0’ as long as the clock pulse
(or CP) isSYMBOL
logic ‘0’, regardless of the S and R input values. When the clock pulse
goes to logic ‘1’, information from the S and R inputs passes through to the
basic flip-flop. With both S= 1 and R= 1, the occurrence of a clock pulse causes
both outputs to momentarily go to logic ‘0’.
When the clock pulse is removed, the state of the flip-flop is indeterminate, i.e.,
either state may result, depending on whether the set or reset input of the flip-
flop remains logic ‘1’ longer than the transition to logic ‘0’ at the end of the
pulse.
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 TRUTH TABLE TIMING DIAGRAM
INPUT CLOCK OUTPUT
S R Q
0 0 0 Not Changing
0 0 1 Not Changing
0 1 0 Not Changing
0 1 1 0
1 0 0 Not Changing
1 0 1 1
1 1 0 Not Changing
1 1 1 Invalid

*Assuming initial condition: S = 0, R = 0, Q = 0 , build a time

based on sequential value below:
diagram
CLK 1, S = 0; R = 0 ; Q =

CLK 2, S = 0; R = 1 ; Q =

CLK 3, S = 1; R = 0 ; Q =

CLK 4, S = 0; R = 1 ; Q =
 
Once Q is determined, is easily found since it is simply the complement of Q.
If clock is in 0, the flip flop will not change even though S and R have changes.
CLK 5, S = 1; R = 0 ; Q = 11
 TIMING DIAGRAM

TRUTH TABLE

INPUT CLOCK OUTPUT

S R Q
0 0 1 Not Changing
0 1 1 0
1 0 1 1
1 1 1 Invalid

*Assuming initial condition: S = 0, R = 0, Q = 0 , build a time

based on sequential value below:
diagram
CLK 1, S = 0; R = 0 ; Q =

CLK 2, S = 0; R = 1 ; Q =

CLK 3, S = 1; R = 0 ; Q =

CLK 4, S = 0; R = 1 ; Q =
 
Once Q is determined, is easily found since it is simply the complement of Q.
If clock is in 0, the flip flop will not change even though S and R have changes.
CLK 5, S = 1; R = 0 ; Q = 11
C) JK Flip-Flop

INPUT CLOCK OUTPUT

J K Q
0 0 1 Not Changing
0 1 1 0
1 0 1 1
1 1 1 TOGGLE

TRUTH TABLE
C) JK Flip-Flop Timing Diagram
d) T- FLIP-FLOP

CLOCK T
1 0 HOLD
1 1

TRUTH TABLE

TIMING DIAGRAM
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 e) D-Flip-Flop

CLOCK D
1 0 0
1 1

TRUTH TABLE

24
2.3.6 Describe Register
As an example of the use of flip-flops, let us first
examine one of the essential elements of the
CPU: the register. As we know, a register is a
digital circuit used within the CPU to store one
or more bit of data.

Two basic types of register are commonly used:

parallel registers and shift register.
a) SHIFT REGISTER
A shift register accepts and/or transfer information serially. Eg:
Figure below shows a 4-bit shift register constructed from
clocked D flip-flops. Data are input only to the leftmost flip-flop.
With each clock pulse, data are shifted to the right one position,
and the rightmost bit is transferred out. Shift registers can be
used to interface to serial I/O devices. In addition, they can be
used within the ALU to perform logical shift and rotate function.
This figure illustrates entry of the four bits
1010 into the register, beginning with the
right-most bit. The register is initially clear.
The 0 is put into the data input line, making D
= 0 for FF0. When the first clock pulse is
applied, FF0 is RESET, thus storing the 0.

Next the second bit, which is a 1, is applied to

the data input, making D = 1 for FF0 and D = 0
for FF1 because the D input of FF1 is
connected to the Q0 output. When the
second clock pulse occurs, the 1 on the data
input is shifted into FF0 because FF0 sets, and
the 0 that was in FF0 is shifted into FF1.

The third bit, a 0, is now put onto the data-

input line, and a clock pulse is applied. The 0
is entered into FF0, the 1 stored in FF0 is
shifted into FF1, and the 0 stored in FF1 is
shifted into FF2.

The last bit, a 1, is now applied to the data

input, and a clock pulse is
applied. This time the 1 is entered into FF0,
the 0 stored in FF0 is shifted into FF1, the 1
stored in FF1 is shifted into FF2, and the 0
stored in FF2 is shifted into FF3. This
completes the serial entry of the four bits into
the shift register, where they can be stored
for any length of time as long as the flip-flops
have DC power.
b) Parallel Register
For parallel in/parallel out shift registers, all data bits appear on
the parallel outputs immediately following the simultaneous
entry of the data bits. The following circuit is a four-bit parallel
in/parallel out shift register constructed by D flip-flops.
The D's are the parallel inputs and the Q's are the parallel
outputs. Once the register is clocked, all the data at the D inputs
appear at the corresponding Q outputs simultaneously.
2.3.7 Memory organisation
Building large memories required a different organization, one in which individual
words can be addressed. A widely-used memory organization that meets this
criterion is shown in the next figure. This example illustrates a memory with four 3-
bit words. Each operation reads or writes a full 3-bit word. While the total memory
capacity of 12 bits is hardly more than our octal flip-flop, it requires fewer pins and
most important, the design extends easily to large memories.

It has eight input lines and three output lines. Three inputs are data: I0 , I1, and I2 ;
two are for the address: A0 and A1 ; and three are for control: CS for Chip Select, RD
for distinguishing between read and write, and OE for Output Enable. The three
outputs are for data: O0, O1, and O2 . In principle this memory could be put into a
14-pin package, including power and ground versus 20 pins for the octal flip-flop.

To select this memory chip, external logic must set CS high and also set RD
high (logical 1) for read and low (logical 0) for write. The two address lines must
be set to indicate which of the four 3-bit words is to be read or written. For a read
operation, the data input lines are not used, but the word selected is placed on the
data output lines. For a write operation, the bits present on the data input lines are
loaded into the selected memory word; the data output lines are not used.