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William Stallings Computer Organization and Architecture 7 Edition Instruction Sets: Addressing Modes and Formats

The document discusses different addressing modes and instruction formats. It describes seven common addressing modes - immediate, direct, indirect, register, register indirect, displacement (indexed), and stack. It provides examples and diagrams to illustrate each mode. The document also discusses different instruction formats used in processors like PDP-8, PDP-10, Pentium, and PowerPC. It notes the tradeoffs involved in allocating bits between the number of opcodes, operands, addressing modes, and address range supported in the instruction set.

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102 views45 pages

William Stallings Computer Organization and Architecture 7 Edition Instruction Sets: Addressing Modes and Formats

The document discusses different addressing modes and instruction formats. It describes seven common addressing modes - immediate, direct, indirect, register, register indirect, displacement (indexed), and stack. It provides examples and diagrams to illustrate each mode. The document also discusses different instruction formats used in processors like PDP-8, PDP-10, Pentium, and PowerPC. It notes the tradeoffs involved in allocating bits between the number of opcodes, operands, addressing modes, and address range supported in the instruction set.

Uploaded by

Alaa Younis
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© © All Rights Reserved
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Download as PPT, PDF, TXT or read online on Scribd
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William Stallings

Computer Organization
and Architecture
7th Edition

Chapter 11
Instruction Sets:
Addressing Modes and Formats
Addressing Modes
• Immediate
• Direct
• Indirect
• Register
• Register Indirect
• Displacement (Indexed)
• Stack
Immediate Addressing
• Operand is part of instruction
• Operand = address field
• e.g. ADD 5
—5 is operand
—Add 5 to contents of accumulator
• The simplest form of addressing is immediate addressing
• No memory reference to fetch data (saving one memory
• or cache cycle in the instruction cycle)
• Fast
• The disadvantage is that the size of the number is restricted
to the size of the address field
Immediate Addressing Diagram

Instruction
Opcode Operand
Direct Addressing
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
—Add contents of cell A in the memory to accumulator
—Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective
address
• Limited address space:
The length of the address field is usually less than the
word length, thus limiting the address range
Direct Addressing Diagram

Instruction
Opcode Address A
Memory

Operand
Indirect Addressing (1)
• Memory cell pointed by address field contains the
address of (pointer to) the operand
• EA = (A)
—Look in A, find address (A) and look there for operand
• e.g. ADD (A)
—Add contents of cell pointed to by contents of A to
accumulator
Indirect Addressing (2)
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded
—e.g. EA = (((A)))
– Draw the diagram yourself
• Multiple memory accesses to find operand
• Hence slower
Indirect Addressing Diagram

Instruction
Opcode Address A
Memory

Pointer to operand

Operand
Register Addressing (1)
• Operand is held in register named in
address filed
• EA = R
• Limited number of registers
• Very small address field needed
—Shorter instructions:
An address field that references registers will
have from 3 to 5 bits, so that a total of from 8
to 32 general-purpose registers can be
referenced
—Faster instruction fetch
Register Addressing (2)
• No memory access
• Very fast execution
• Very limited address space
• Multiple registers helps performance
—Requires good assembly programming or
compiler writing
• Direct addressing
Register Addressing Diagram

Instruction
Opcode Register Address R
Registers

Operand
Register Indirect Addressing
• Similar to indirect addressing
• EA = (R)
• Operand is in memory cell pointed by
contents of register R
• Large address space (2n)
• One fewer (less) memory access than
indirect addressing
Register Indirect Addressing Diagram

Instruction
Opcode Register Address R
Memory

Registers

Pointer to Operand Operand


Displacement Addressing
• EA = A + (R)
• Address field hold two values
—A = base value (direct addressing)
—R = register that holds displacement
Displacement Addressing Diagram

Instruction
Opcode Register R Address A
Memory

Registers

Pointer to Operand + Operand


Relative Addressing
• A version of displacement addressing
• R = Program counter, PC
• EA = A + (PC)
• That is, the next instruction address is added to
the address field to produce the EA.
• c.f locality of reference & cache usage
• If most memory references are relatively near
to the instruction being executed, then the use
of relative addressing saves address bits in the
instruction
Base-Register Addressing
• A holds displacement
• R holds pointer to base address
• R may be explicit or implicit
• e.g. segment registers in 80x86
Indexed Addressing
• A = base
• R = displacement
• EA = A + R
• Good for accessing arrays
—EA = A + R
—R++
Indexed Addressing

• An important use of indexing is to provide an efficient


mechanism for performing iterative operations.
• Consider, for example, a list of numbers stored starting at
location A. Suppose that we would like to add 1 to each
element on the list. We need to fetch each value, add 1 to it,
and store it back.
• The sequence of effective addresses that we need is A, A+1,
A . . +2., up to the last location on the list. With indexing, this
is easily done.
• The value A is stored in the instruction’s address field, and the
chosen register, called an index register, is initialized to 0.
After each operation, the index register is incremented by 1.
Auto indexing
• EA = A + (R)
• (R) = (R) + 1

• If general-purpose registers are used, the


auto index operation may need to be
signaled by a bit in the instruction.
Combinations
• Both indirect addressing and indexing are used together.

• Post-indexing:
EA = (A) + (R)
First, the contents of the address field are used to access a memory
location containing a direct address. This address is then indexed by
the register value

• Pre-index (the indexing is performed before the indirection)


EA = (A+(R))
Stack Addressing
• Operand is (implicitly) on top of stack
• The stack mode of addressing is a form of implied addressing.
The machine instructions need not include a memory
reference but implicitly operate on the top of the stack.

• e.g.
—ADD Pop top two items from stack
and add
Conclusion
Pentium Addressing Modes
• Virtual or effective address is offset into segment
— Starting address plus offset gives linear address
— This goes through page translation if paging enabled
• 12 addressing modes available
— Immediate
— Register operand
— Displacement
— Base
— Base with displacement
— Scaled index with displacement
— Base with index and displacement
— Base scaled index with displacement
— Relative
Pentium Addressing Modes
• For the immediate mode, the operand is included in the
instruction. The operand can be a byte, word, or doubleword
of data.

• For register operand mode, the operand is located in a


register. For general instructions, such as data transfer,
arithmetic, and logical instructions, the operand can be one of
the 32-bit general registers (EAX, EBX, ECX,EDX,ESI, EDI,
ESP, EBP),
• One of the 16-bit general registers (AX, BX, CX, DX, SI, DI,
SP, BP), or one of the 8- bit general registers (AH, BH, CH,
DH, AL, BL, CL, DL).
PowerPC Addressing Modes
• Load/store architecture:
Load and store instructions are the only instructions that reference
memory. This is always done indirectly through a base register plus
Offset
PowerPC Addressing Modes

Offset:

For this addressing method, indexing is not used. An offset value is added to the
value in the base register to form the memory address. As an example Figure 11.3a
illustrates this method with the assembly language instruction
STRB r0, [r1, #12].
PowerPC Addressing Modes

Pre-index:

The memory address is formed in the same way as for offset addressing.
The memory address is also written back to the base register
PowerPC Addressing Modes

Post-index:

The memory address is the base register value. An offset is added to


the base register value and the result is written back to the
base register
PowerPC Addressing Modes
• Branch address
—The only form of addressing for branch instructions is
immediate addressing
• Arithmetic
—Operands in registers or part of instruction
—Floating point is register only
Instruction Formats
• trade-off here is between the design for a
powerful instruction set and a need to save
space
• Programmers want more opcodes, more
operands, more addressing modes, and greater
address range
• Includes opcode
• Includes (implicit or explicit) operand(s)
• Usually more than one instruction format in an
instruction set
Instruction Formats
• More opcodes and more operands make life easier for the
programmer: shorter programs can be written to
accomplish given tasks.
• More addressing modes give the programmer greater
flexibility
• With the increase in main memory size and the increasing
use of virtual memory, programmers want to be able to
address larger memory ranges
• All of these things (opcodes, operands, addressing modes,
address range) push in the direction of longer instruction
lengths
• Longer instruction length may be wasteful
Instruction Length
• Affected by and affects:
—Memory size
—Memory organization
—Bus structure
—CPU complexity
—CPU speed
• Trade off between powerful instruction set
and saving space
Allocation of Bits
• Number of addressing modes

• Number of operands
• Register versus memory:
With a single user-visible register
(usually called the accumulator), one operand address is
implicit and consumes no instruction bits

With multiple registers, only a few bits are needed to specify


the register. The more that registers can be used for
operand references, the fewer bits are needed
Allocation of Bits
Number of register sets:
For example, with two sets of eight registers, only
3 bits are required to identify a register; the
opcode or mode register will determine which set of
registers is being referenced.
•Address range
•Address granularity:
For addresses that reference memory rather than
registers, another factor is the granularity of addressing.
In a system with 16- or 32-bit words, an address can
reference a word or a byte at the designer’s choice
PDP-8 Instruction Format
PDP-10 Instruction Format

• The opcode occupies 9 bits, allowing up to 512


operations
• 18 bit for memory address
PDP-11 Instruction Format
VAX Instruction Examples
Pentium Instruction Format
PowerPC Instruction Formats (1)
PowerPC Instruction Formats (2)
Foreground Reading
• Stallings chapter 11
• Intel and PowerPC Web sites
EXAMPLE
 What is the number of bits required to design an instruction
format according to the following
 The number of instructions is 21 instructions
 We want to support 5 addressing modes (register direct,
register indirect, direct , indirect)
 The number of registers is 9 registers
 The memory size is 4 KB
 Instruction has two operands
 Support direct access to the whole memory

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