Computer Organization and Architecture

Designing for Performance

11th Edition

Chapter 14
Instruction Sets:
Addressing Modes and
Formats
Addressing Modes

Immediate

Direct

Indirect

Register

Register indirect

Displacement

Stack
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Figure 14.1
Addressing Modes

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Table 14.1
Basic Addressing Modes
Mode Algorithm Principal Advantage Principal Disadvantage

Immediate Operand = A No memory reference Limited operand magnitude

Direct EA = A Simple Limited address space

Indirect EA = (A) Large address space Multiple memory references

Register EA = R No memory reference Limited address space

Register indirect EA = (R) Large address space Extra memory reference

Displacement EA = A + (R) Flexibility Complexity

Stack EA = top of stack No memory reference Limited applicability

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Immediate Addressing
• Simplest form of addressing
• Operand = A
• This mode can be used to define and use constants or set
initial values of variables
– Typically the number will be stored in twos complement form
– The leftmost bit of the operand field is used as a sign bit

• Advantage:
– No memory reference other than the instruction fetch is required to obtain the
operand, thus saving one memory or cache cycle in the instruction cycle

• Disadvantage:
– The size of the number is restricted to the size of the address field, which, in
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most instruction sets, is small compared with the word length
Direct Addressing
Address field
contains the
effective address
of the operand

Effective address
(EA) = address
field (A)

Was common in
earlier
generations of
computers

Requires only one

memory
reference and no
special
calculation

Limitation is that
it provides only a
limited address
space
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Indirect Addressing
• Reference to the address of a word in memory which contains a full-
length address of the operand
• EA = (A)
– Parentheses are to be interpreted as meaning contents of

• Advantage:
– For a word length of N an address space of 2N is now available

• Disadvantage:
– Instruction execution requires two memory references to fetch the operand
▪ One to get its address and a second to get its value

▪ A rarely used variant of indirect addressing is multilevel or cascaded indirect

addressing
– EA = ( . . . (A) . . . )
– Disadvantage is that three or more memory references could be required to fetch an operand

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Register Addressing

Address field
refers to a
register rather
EA = R
than a main
memory
address

Advantages: Disadvantage:
• Only a small • The address
address field is space is very
needed in the limited
instruction
• No time-
consuming
memory
references are
required
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Register Indirect Addressing
• Analogous to indirect addressing
– The only difference is whether the address field refers to a memory
location or a register

• EA = (R)
• Address space limitation of the address field is overcome
by having that field refer to a word-length location
containing an address
• Uses one less memory reference than indirect
addressing

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Displacement Addressing
• Combines the capabilities of direct addressing and register
indirect addressing
• EA = A + (R)
• Requires that the instruction have two address fields, at least one
of which is explicit
– The value contained in one address field (value = A) is used directly
– The other address field refers to a register whose contents are added to A to
produce the effective address

• Most common uses:

– Relative addressing
– Base-register addressing
– Indexing
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 Relative Addressing

The implicitly referenced register is the program counter

(PC)
• The next instruction address is added to the address field to produce
the EA
• Typically the address field is treated as a twos complement number for
this operation
• Thus the effective address is a displacement relative to the address of
the instruction
Exploits the concept of locality

Saves address bits in the instruction if most memory

references are relatively near to the instruction being
executed
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Base-Register Addressing
• The referenced register contains a main memory address and
the address field contains a displacement from that address
• The register reference may be explicit or implicit
• Exploits the locality of memory references
• Convenient means of implementing segmentation
• In some implementations a single segment base register is
employed and is used implicitly
• In others the programmer may choose a register to hold the
base address of a segment and the instruction must reference
it explicitly
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Indexing
• The address field references a main memory address and the referenced register
contains a positive displacement from that address
• The method of calculating the EA is the same as for base-register addressing

• An important use is to provide an efficient mechanism for performing iterative

operations
• Autoindexing
– Automatically increment or decrement the index register after each reference to it
– EA = A + (R)
– (R) (R) + 1

• Postindexing
– Indexing is performed after the indirection
– EA = (A) + (R)

• Preindexing
– Indexing is performed before the indirection 13
– EA = (A + (R))
Stack Addressing
• A stack is a linear array of locations
– Sometimes referred to as a pushdown list or last-in-first-out queue
• A stack is a reserved block of locations
– Items are appended to the top of the stack so that the block is partially filled
• Associated with the stack is a pointer whose value is the address of the top of
the stack
– The stack pointer is maintained in a register
– Thus references to stack locations in memory are in fact register indirect
addresses

• Is a form of implied addressing

• The machine instructions need not include a memory

reference but implicitly operate on the top of the stack

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Figure 14.2
x86 Addressing Mode Calculation

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Table 14.2
x86 Addressing Modes
Mode Algorithm
Immediate Operand = A
Register Operand LA = R
Displacement LA = (SR) + A

Base LA = (SR) + (B)

Base with Displacement LA = (SR) + (B) + A

Scaled Index with Displacement LA = (SR) + (I) × S + A

Base with Index and Displacement LA = (SR) + (B) + (I) + A
Base with Scaled Index and Displacement LA = (SR) + (I) × S + (B) + A
Relative LA = (PC) + A

LA = linear address R = register

(X) = contents of X B = base register
SR = segment register I = index register
PC = program counter S = scaling factor
A = contents of an address field in the instruction

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Figure 14.3
ARM Indexing Methods

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ARM Data Processing Instruction Addressing
and Branch Instructions

• Data processing instructions

– Use either register addressing or a mixture of register and immediate
addressing
– For register addressing the value in one of the register operands
may be scaled using one of the five shift operators

• Branch instructions
– The only form of addressing for branch instructions is immediate
– Instruction contains 24 bit value
▪ Shifted 2 bits left so that the address is on a word boundary
▪ Effective range ± 32MB from from the program counter

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Figure 14.4
ARM Load/Store Multiple Addressing

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Instruction Formats

Must include an
Define the layout opcode and, For most
of the bits of an implicitly or instruction sets
instruction, in explicitly, more than one
terms of its indicate the instruction
constituent fieldsaddressing mode format is used
for each operand

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Instruction Length
• Most basic design issue
• Affects, and is affected by:
– Memory size
– Memory organization
– Bus structure
– Processor complexity
– Processor speed

• Should be equal to the memory-transfer length or one should be a

multiple of the other

• Should be a multiple of the character length, which is usually 8 bits,

and of the length of fixed-point numbers
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Allocation of Bits

Number of Register
Number of
addressing versus
operands
modes memory

Number of
Address Address
register
range granularity
sets

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Figure 14.5
PDP-8 Instruction Formats

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Figure 14.6
PDP-10 Instruction Format

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Variable-Length Instructions
• Variations can be provided efficiently and compactly
• Increases the complexity of the processor
• Does not remove the desirability of making all of the
instruction lengths integrally related to word length
– Because the processor does not know the length of the next
instruction to be fetched a typical strategy is to fetch a number of
bytes or words equal to at least the longest possible instruction
– Sometimes multiple instructions are fetched

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Figure 14.7
Instruction Formats for the PDP-11

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Figure 14.8
Example of VAX Instructions

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Figure 14.9
x86 Instruction Format

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Figure 14.10
ARM Instruction Formats

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Figure 14.11
Examples of Use of ARM Immediate
Constants

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Figure 14.12
Expanding a Thumb ADD Instruction into
its ARM Equivalent

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Thumb-2 Instruction Set
• The only instruction set available on the Cortex-M microcontroller
products
• Is a major enhancement to the Thumb instruction set architecture (ISA)
– Introduces 32-bit instructions that can be intermixed freely with the older 16-bit Thumb
instructions
– Most 32-bit Thumb instructions are unconditional, whereas almost all ARM instructions can
be conditional
– Introduces a new If-Then (IT) instruction that delivers much of the functionality of the
condition field in ARM instructions

• Delivers overall code density comparable with Thumb, together with the
performance levels associated with the ARM ISA
• Before Thumb-2 developers had to choose between Thumb for size and
ARM for performance

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Figure 14.13
Thumb-2 Encoding

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 • Instruction Sets:
Summary Addressing Modes
and Formats
Chapter 14
• x86 addressing modes
• Addressing modes • ARM addressing modes
– Immediate addressing
– Direct addressing • Instruction formats
– Instruction length
– Indirect addressing
– Allocation of bits
– Register addressing
– Variable-length
– Register indirect instructions
addressing
– Displacement • X86 instruction formats
addressing • ARM instruction formats
– Stack addressing
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