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3 Architecture of 8086

The 8086 CPU has two main units that operate in parallel: 1. The Bus Interface Unit (BIU) handles fetching instructions and data from memory and I/O and writing data back. 2. The Execution Unit decodes and executes instructions using a 16-bit ALU, four 16-bit registers, and a flag register. It employs a parallel RISC-like design using a pipeline of fetch, decode, and execute stages to improve performance.

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52 views25 pages

3 Architecture of 8086

The 8086 CPU has two main units that operate in parallel: 1. The Bus Interface Unit (BIU) handles fetching instructions and data from memory and I/O and writing data back. 2. The Execution Unit decodes and executes instructions using a 16-bit ALU, four 16-bit registers, and a flag register. It employs a parallel RISC-like design using a pipeline of fetch, decode, and execute stages to improve performance.

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Sudeeksha Ganguli
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ARCHITECTURE OF 8086

8086 INTERNAL
ARCHITECTURE
8086 employs parallel processing
8086 CPU has two parts which operate at the same time
Bus Interface Unit
Execution Unit
CPU functions
1. Fetch

2. Decode
3. Execute
BUS INTERFACE UNIT
(BIU)
 Sends out addresses of memory or I/O ports
 Fetches Instructions from memory
 Reads data from memory and Input/Output ports
 Writes data to memory and Input/Output ports

BIU handles all transfers of data and addresses on the


buses required by the Execution Unit
EXECUTION UNIT

Tells BIU (addresses) where to fetch instructions or data


Decodes & Executes instructions
EXECUTION UNIT
Main components are
• Instruction Decoder
• Control System
• Arithmetic Logic Unit
• General Purpose
Registers
• Flag Register
• Pointer & Index registers
Instruction Decoder
Translates instructions fetched from memory into a series of
actions, which EU carries out

Control System
Generates timing and control signals to perform the internal
operations of the microprocessor

Arithmetic Logic Unit


EU has a 16-bit ALU which can ADD, SUBTRACT, AND, OR,
increment, decrement, complement or shift binary numbers
GENERAL PURPOSE
REGISTERS
Four 16-bit general-purpose
registers (AX, BX, CX and DX).
Registers used for arithmetic,
logical instructions and temporary
storage.
16-bit registers is further
subdivided into two 8-bit registers
(upper and lower bytes)
AX REGISTER
Accumulator register
Used for arithmetic or logical instructions
Used in Multiplication and Division operations
 Used in I/O operations

BX REGISTER
 used as base register
Holds the base address of the program such as offset address
in indirect addressing mode.
CX REGISTER
Used as count register
counts the number of iterations in loops, and in strings
operations, it specifies the number of characters in a
particular string.

DX REGISTER
data register holds overflow and I/O addresses.
used in combination with AX register to store 32-bit results
of multiplication and division.
FLAG/STATUS REGISTER
 8086 has a 16-bit flag register which indicates the state of the
processor.
It has 9 flags and they are divided into 2 groups − Conditional or
Status Flags and Control Flags.
Conditional or Status Flags: six flags, set or reset by EU on the
basis of results of some arithmetic operations.
Control flags – three flags, used to control certain operations of the
processor
CF-Carry Flag
CF=1, when there is a carry
out of MSB in case of addition
or a borrow in case of
subtraction.
CF=0 otherwise

PF - Parity Flag
PF=1, if result of the operation
contains even number of 1’s
PF=0 otherwise (for odd
number of 1s)
AF- Auxiliary Carry Flag:
AF=1, if there is a carry from the lowest nibble, i.e, bit three during
addition, or borrow for the lowest nibble, i.e, bit three, during
subtraction
AF=0, otherwise
Used in BCD opeartions

ZF- Zero Flag:


ZF=1, if the result of the computation or comparison performed by the
previous instruction is zero.
ZF=0. for non zero result
SF- Sign Flag
SF=1, when the result of any computation is negative.
TF - Trap Flag
TF=1, This flag is used for on-chip debugging. Setting trap flag puts the
microprocessor into single step mode for debugging. In single stepping,
the microprocessor executes a instruction and enters into single step ISR.
If trap flag is set (1), the CPU automatically generates an internal
interrupt after each instruction, allowing a program to be inspected as it
executes instruction by instruction.
If trap flag is reset (0), no function is performed.
IF- Interrupt Flag
IF=1, the maskable interrupt INTR of 8086 is enabled 
IF=0, zero, the interrupt is disabled.
DF: DIRECTION FLAG
Used in string operations
DF=1, string bytes accessed from memory address in
decrement order(from highest address to lowest address)
DF=0, string bytes accessed from memory address in
increment order(from lowest address to highest address)
OF: OVERFLOW FLAG
OF=1, if an overflow occurs, i.e, if the result of a signed
operation is large enough to accommodate in a destination
register.
POINTER AND INDEX
REGISTER
 Stack pointer –Used to hold the top of the stack
segment address. Used during PUSH, POP, CALL
instructions etc.
 Base Pointer – Holds the address of any location
within stack segment. To access random locations in
the stack.
 Source Index – Holds offset address of data segment
during string operations
 Destination index – Holds the offset address of extra
segment during string operations
BUS INTERFACE UNIT (BIU)
Main Components are
• Instruction Queue
• Address Generation Circuit
• Segment Registers
• Instruction Pointer
INSTRUCTION QUEUE
BIU gets upto 6 bytes of next instructions and stores them in
instruction queue.
When EU executes instructions and is ready for its next instruction,
it simply reads the instruction from the instruction queue in BIU.
ADDRESS GENERATION CIRCUIT

 Calculates the 20 bit physical address in the memory so that


microprocessor can fetch instructions.

Physical Address = Segment Address x 10H + Offset


Address.
PHYSICAL ADDRESS
CALCULATION
SEGMENT REGISTER
Each segment thus contains 64 KB of
memory and can addressed by 16 bit
segment register
Code segment
 used for addressing memory location
where program stored for execution
Stack segment
used for addressing stack segment of
memory in which stack data is stored.
CPU uses the stack for temporarily storing
data
Data segment and Extra segment
points to the data segment of the memory,
where data is stored.
INSTRUCTION POINTER

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