INTEGRATED ANALOG/DIGITAL

BICMOS PROCESS
&
DEEP SUBMICRON PROCESSES

Presented by
M.ABHIRAM
MTECH-VLSI(1/2)
321206540005
Integrated analog or digital BICMOS process
• BICMOS technology is advancing day by day, the primary concern of which
starting technology either to use Bipolar or CMOS is a major concern
• Bipolar oriented processes make use of thick epitaxial layers and deep P+
isolation that suffer from poor packing density
• On the other hand, the n-well CMOS process allow the npn collector region to be
self isolating with the p-epitaxial layer acting as isolation region
• BICMOS means integrating the bipolar technology in the existing CMOS
technology (to achieve the high driving capability from bipolar and low power
dissipation from CMOS technology)
• Now lets discuss about the n-well CMOS orientation process
Consideration for process integration
• Care must be taken while fabricating the necessary bipolar process into the
existing CMOS process such that original CMOS parameters remains same
(CMOS parameters such as both electrical I-V data as well as the layout rules)
The major process decision that must be taken while integrating the bipolar steps
are:-
1.Types of n+ buried layers needed
2. Requirement on p-epitaxial layer thickness to support the bipolar operating
voltage
3. Where to add deep n+ collector diffusion
4. Whether to use the source/drain regions as emitter and base regions
5. Where to integrate the separate emitter and base operations if the needed
• The heat associated with n+ buried layers does not effect the CMOS device as it is
the first module in the device
• To achieve the low packing density and the low npn substrate resistance, a shallow
and highly doped n+ region is desired
• The typical sheet resistance value is20 ohms/ square and the junction depth is of
2.5 micrometer respectively
• The resistivity and the thickness requirement for the epitaxial layer effects the
both bipolar and CMOS device characteristics
• So resistance must be observed properly so that it does not increases and we must
take necessary measures to reduce the resistance and determination of epitaxial
layer thickness is also very important
• Use of antimony results in possibility of n-layer auto doping in the p epitaxial
layer
• Determination of epitaxial layer thickness is very difficult due to its dependence
on following factors :
• It depends on the
1. The n-well junction depth
2. The n-well doping level
3. The n+ buried layer up-diffusion
4. The amount of p-epitaxial layer removed through subsequent oxidations
5. The maximum allowable npn
6. The maximum operating voltage
Choosing the thickness of p-epitaxial layer
• To form low resistance NPN collector  n-well must extend down to contact the n+
buried layer
• So maximum epitaxial thickness for a given n-well depth is shown in the figure 1

FIG 1: Maximum BICMOS P-epitaxial thickness as a function of CMOS n-well diffusion depth
• Here due to oxidation 1.0 micrometer of the p-epitaxial layer was removed can be seen
from the fig 1
• For a heavily doped shallow n+ buried layer process, the amount of up diffusions of the
order 80 to 100% of the junction well depth
• The operating voltage of npn BJT is limited to BV breakdown mechanism and it is given
by

Here B(plane) is the collector-base breakdown voltage

Parameter n has typical value of 3 to 6
The B(plane) in the equation refers to non-curvature limited collector-base breakdown
voltage along the planar region of the base which is under the emitter region
• This calculation portion of collector-base junction is important because the
majority of the collector current flows across this region of the junction
• Due to curvature and channel stop doping effect, the actual B of the device is
lower than the B(plane)
• From the above B equation, the hfe and B are set by design requirements then the
B(plane) can be calculated
For example: assume a hypothetical process which requires the operating voltage of
15v, with a maximum hfe of 150 which would need a minimum B(plane) of 54v at
n=4
• Mainly the n-well and base process are set by other factors such as CMOS
compatibility
• The epitaxial layer is the main variable in determining B(plane)
• As the epitaxial layer thickness is reduced from its maximum, the vertical distance
between the base and buried collector diffusion is reduced, which lowers the B(plane)

Fig 2: B(plane) as a function of epitaxial layer thickness for 4.5 micrometer n-well process
• We can observe in fig 2 that the effect of p-epitaxial layer thickness on the
B(plane) on a particular n-well process
For example: from fig 2, if the minimum epitaxial layer thickness is of 7.0
micrometer then the minimum B(plane) of greater than 50V can be observed
• The high current npn transistors are used in analog design and these require deep
n+ collector diffusions to lower the collector resistance of lightly doped n-well
• These deep diffusions are generally as deep as epitaxial layer thickness and
require high temperature processing
• The diffusions are done before the channel stop to prevent additional heating
which effects the CMOS device performance
Cont..

• Mos transconductance can be reduced by make use of source/drain regions for

bipolar emitter and base regions through increased source/drain sheet resistance
• The base diffusion is often produces the heat cycles so we implement before
channel stop implants but this reduces the bipolar self-alignment
• The emitter operation is generally performed near the end of the process to
minimize process variability which results in poor control (Bipolar current
gain, Unity gain frequency)
Typical analog/digital BICMOS process
1.The process begins with a p-type substrate
After oxidation, n+ buried layers are defined
For buried layers here we use antimony type (as it is n type we can use phosphorus,
arsenic and antimony. Any one from three can be use to define it and it is n+ so heavily
doped)
By use of implantation and diffusion steps antimony buried layers are formed
The surface oxide is stripped to make the structure into even surface so that photoresist
layers can be defined easy in further steps

Fig for the step 1(a): formation of n+ buried layers

2. The wafer surface is treated with short hydrochloric acid (HCL) etch to remove
any defects
Next step is P-epitaxial layer deposition
Wafer is re-oxidised and windows are defined for n-well regions to be performed
For n-well the phosphorus ion implantation is done to form n-well
The n+ collector region are formed by the n+ collector heat cycle, using phosphorus
dopants which helps us to complete the n-well drive in

Fig for step 2: (b)Formation of n-well and n+ collector regions with the p-epitaxial deposition
Cont..

• After formation of n-well and n+ collector regions, the surface oxide is stripped
and a thin pad oxide is grown
3. By use of boron ion implantation, base regions for the npn bipolar transistor is
patterned (base is formed earlier in the process because this process produces more
heat which should not effect the existing characteristics)
This ion implantation is diffused in an inert ambient to anneal the silicon for
improved bipolar transistor performance. This step helps in reduction of base
resistance
 Fig for step 3: (c)Formation of npn bipolar base region
(Here we formed p-type base in the second n-well where bipolar technology is
implemented so boron ion implantation is done and resist layer is formed before performing
ion implantation to protect the wafer and where we want the base region we etch that part
and ion implantation is done in that etched part and thin oxide layer is under the resist to
support it)
Cont..

• Next a nitride film is deposited over the pad oxide and active mask is used to
define this region
4. After etching the nitride, a blanket phosphorus channel stop implant is carried out
to increase the threshold voltage of pMOS devices
• Another masking step is used, where a boron channel stop implant is performed
to increase the threshold voltage of nMOS devices
• After stripping the photo resist, a 1m thick field oxide is grown in non-active
regions
 Fig for step 4: (d) formation of moat regions and subsequent channel stop implants
The nitride and underlying pad oxide are removed followed by the growth of thin
oxide layer approx. 350 to 500 A
The threshold adjust implant is carried is carried out
5.The first level poly silicon (poly-1) is next deposited, doped, patterned and etched
to form the MOS gate electrodes and bottom plates of poly-poly capacitors

Fig for step-5: (e)formation of first poly silicon layer for CMOS gates and MOS capacitor
• A 30 to 100nm thick capacitor interlevel dielectric is formed next over the poly-1 layer by
utilising either an oxide-nitride-oxide film or an oxide alone layer
• The second poly silicon layer is deposited and doped to form a high sheet resistance film
that can fabricate high valued resistors and remaining layer is n+ doped which is used to
form top level capacitor

Fig: (f)Definition and deposition of second polysilicon layer for resistors and top level capacitor
plates
 Fig: (g) formation of poly-2 for resistor and top capacitor plates
The remaining portion of process flow follows conventional CMOS and bipolar
device formation
• First we form LDD(low diffused drain) regions for nMOS transistor using
phosphorus implantation can be observed form fig h

Fig (h): Formation of LDD nmos source/drain regions and oxide wall spacers
(Low diffused drain structures are used to lower the hot carrier effect)
• Next n+ and p+ source/ drain regions are formed independently with arsenic and
boron implants from fig i

Fig (i): Formation of CMOS source/ drain regions and bipolar base contact region
• These implants are offset from the gate by sidewall spacers which helps to reduce
the overlap capacitance
• Then with photoresist mask, the bipolar emitter and collector contact regions are
formed using phosphorus implant step

Fig (j): Formation of directly implanted n+ emitter and collector contact regions
Cont..

• In this process we do not use poly-silicon emitter because they provide high
emitter contact resistance than directly implanted emitter
• The last part of the process is to form contact holes and metal interconnections
DEEP SUBMICRON PROCESS
• Earlier the BICMOS process integration require only 3 to 4 additional masking
steps to the standard CMOS process and it has low performance non-self aligned
npn bipolar transistor
• Today modern high performance non-self aligned npn bipolar transistor,
incorporated in modular fashion
• Modularity is the process design for practical approach to satisfy CMOS, Bipolar,
process support and interconnect requirements and increase the integration levels
Polysilicon emitter high performance BICMOS structure:

• This BICMOS structure require 23 masking step which is suitable for 3.3V and
5V
• The structure was built on two poly, two metal wire, twin well 0.6m base line
CMOS process
• To decrease the latchup problem, buried n+ and p+ structures are used in the
process
• Polycide mos gate and polysilicon emitter bipolar were employed
• Isolation process used is LOCOS
Cont…

KEY STEPS:
1. Starting material used is p-substrate with resistivity of 16 to 24 ohm-cm
2. Buried layers used are antimony and boron
3. Epitaxial layer is of n-type with resistivity of 0.6 ohm-cm and thickness of 1.4
m
4. Gate oxide thickness is of 125
5. Polycide is used for both gate and emitter structures
CONT…

FIG: Cross sectional view of polysilicon emitter bipolar structure

FIG: Layout diagram of polysilicon emitter bipolar structure
Cont..
• The key to correct bipolar formation and operation for this technique is to
form polysilicon emitter region
• The first polysilicon emitter technique is introduced in 1979
• By use of polysilicon emitter, the current gain is increased 3 to 7 times
greater than conventional emitter transistor
• The polysilicon emitter allows the holes to be diffused into polysilicon
contact which prevents the recombination at the contacts
• The current gain can be high in shallow emitter regions
• The poly/si interface with oxide barrier serves as recombinational traps
• The emitter drive-step-in is carried out by rapid thermal processing at
1050℃
• This process determines the final emitter/base junction, base width, nature of
poly/si interface
PROCESS FLOW FOR POLYSILICON EMITTER FORMATION:
1. Emitter window etch, light oxidation

2. Oxide dip, poly preclean (HF last), poly emitter deposition

3. As emitter implant

4. Emitter drive-in step (RTP, 1000 ℃ at 30 sec)

Cont…

5. WSIx deposition, poly-cap deposition, poly-2 mask and etch

The 0.6 m polysilicon emitter BICMOS process flow
a) Starting substrate is p-type with resistivity of 16-24 ohm-cm
Initial oxidation forms tox=4500
Up on formation of buried n+ mask, oxide etch (plasma + buffered oxide etch) is
carried out followed by chemical resist strip
After pad oxidation (85 ), buried n+ implant is performed (Antimony type n+
implant with implant dose of 1.60E15 Atom/cm^2, using implant energy of 70
keV at implant angle)
b) After an oxide dip (tox loss 30 ), buried n+ drive-in is carried out at 1150
(tox=1300 )
Buried p+ mask is then used, followed by oxide plasma etch(tox after= 900 )
The buried P+ implant dose is 0.30E14(with 50keV and 7 implant angle)
After that chemical resist strip cum oxide dip (tox loss 30 )
The buried P+ drive-in is performed at 1000 using
This process is completed by an epitaxial preclean step
c) N-epitaxial layer is deposited with -cm, t=1.4 and up diffusion m
Pad oxidation produces a 300 layer
An n-well mask is used next and n-well implantation is developed using phosphorus
at 0.66E13 , with 150 keV and at 7 tilt
Up on chemical resist strip, p field mask (for p well) followed by p-well implant of
boron (of 0.2E13 , with 50 keV and at 7 tilt) is carried out
After chemical resist strip/oxide strip, well drive-in is done at 1150 at tox=150 and
d) The steps involved are:
Oxide dip (tox loss 300 ), pad 2 oxidation (200 ), nitride deposition (1525),
Composite mask nitride plasma etch, n-field implant using phosphorus (at
0.20E13,190keV, 7)
Plasma Chemical resist strip, p-field mask (for p-field), p-field implant ( at
0.60E14 ,80keV, 7), chemical resist strip and field oxidation at 1000, yielding at tox
of 5500
e) The steps used here are:
Oxide dip/nitride strip, sinker/deep collector mask, Sinker implant to give
Chemical resist strip, Oxide dip with tox loss 300 and sinker drive-in at 1000
(using tox=300 , with =1.2 )
 f) The processing sequence here
involves:
Poly-1 deposition (2300 )
high sheet-rho implant
TEOS deposition (2000 )
TEOS densification
resistor mask
TEOS etch
plasma chemical resist strip
Poly-1 doping at 900 for 37 minutes

TEOS- Tetraethyl orthosilicate

g) The steps used here are:
TEOS strip, poly-1 mask (for forming resistor/capacitor), poly-1 etch, plasma
chemical resist strip and poly-1 oxidation (65 )
Cont…

h) The CMOS masking (expose CMOS), Oxide removal (CMOS active area),
Chemical resist strip, gate oxidation (tox=125 ) and amorphous split poly deposition
with tox=600
i) Vt block mask
Vt implant of boron (at 0.19E13) are performed here
J) Upon stripping the resist, base masking and base implant are carried out
The boron implant dosages for 3.3v and 5.0V applications are 0.17E14 and 0.21E14
respectively
Cont…

k) Emitter mask, poly/oxide etch and resist strip are performed

l) Light oxidation producing tox=80 is first performed
After oxide dip (tox loss=300 ), poly-2 deposition gives =1700
Emitter implant (1.2E16) is then carried out
After back etch, emitter drive using RTA at 1010 for 30 minutes is performed
A 1500 thick Wsix layer is next deposited. After poly deposition (500 ), poly-2
mask, poly-2 etch and plasma chemical resist strip are simultaneously done
m) The steps involved here are:
TEOS thin spacer deposition (400 ), nLDD mask (expose nMOS), nLDD implant
(phosphorus, 0.40E14), chemical resist strip, spacer TEOS deposition (2000 ),
spacer etch, spacer oxidation (900), n+ implant mask hard bake, n+ S/D implant and
finally chemical resist strip
n) Lastly the steps carried out are:
P+ implant masking, hard bake, p+ implant, chemical resist strip, low temperature
oxide (LTO) deposition (1000 ), boron phosphate TEOS(BPTEOS) deposition
(10000 ), BPTEOS densification, BPTEOS back etch, sulfuric clean, contact mask,
contact etch, chemical resist strip and final 0.6double metal interconnect process
Cont..

Electrical performance:
The polysilicon emitter bipolar structures are used for both 3.3V and 5V
applications
Now lets discuss about the electrical parameters for the device when operated in
these two voltages and CMOS electrical parameters
The results shows that the polysilicon emitter npn bipolar transistors are able to
achieve (Unity gain frequency) of 13 to 19 GHz and also high current gains when
compared to those with the use of direct metal contacts to the emitter
Electrical parameters of polysilicon emitter npn bipolar structure when
operated at 5V: 5V process (0.6 emitter)
parameter MIN. Typical MAX.
(GHz) 13 15 17
(GHz)* 14 17 20
50 95 140
(v) 12 20 30
(V) 5.3 6.5 10
(V) 12 16 20
(V) 5.5 6.3 7.1

 Unity gain frequency  Bipolar Current Gain factor

 Maximum operating frequency  Forward early voltage

• Electrical parameters of polysilicon emitter npn bipolar structure
when operated at 3.3V:

3.3V process (0.6 emitter)

Parameter Min. Typical Max.
(GHz) 15 17 19
(GHz)* 16 19 22
70 120 180
(v) 8 14 23
(V) 4 6 8
(V) 12 16 20
(V) 6.2 7.0 7.8
• Comparison of the New process flow with the conventional BICMOS
Process
nMOS (0.6) represents 475
nMOS parameter Min. Typical Max.
0.60 0.75 0.90
16 19 22
9 12.7 ---

pMOS(0.6) represents 270

nMOS parameter Min. Typical Max.

-0.95 -0.80 -0.65
-12.8 -10.8 -8.8
------ -10.8 -9.0
Low-Capacitance Bipolar/BICMOS Process:
• In this BICMOS process, an ultra-low capacitance npn bipolar transistor
is incorporated with the conventional 10-GHz, single poly, npn and MOS
devices.
• This process was based on conventional, Single poly, BICMOS process
with inclusion of three additional modules:
1) Shallow and Deep trenches
2) The poly-ridge emitter transistor (PERT)
3) Strap connections to the active areas
• The 0.2wide emitter PERT structure yields low capacitances
(emitter/base: 1.5fF, collector/base: 1fF) and high frequency ability (cut-
off frequency: 14 GHz)
Cont…
Fabrication Process:
In this new process, isolation is achieved using both shallow and deep
trenches
By using these trenches, capacitance can be reduced
Upon defining the both shallow and deep trenches, 30nm of thermal oxide
are introduced for trench filling
A1--thick TEOS layer completes the fills before planarization by CMP
The 3.8--deep trenches, which cut through the buried layer cause the
collector-substrate capacitance to scale down with their dimensions
Now lets compare the new process flow with the standard BICMOS
process and highlight the necessary additional steps
Cont…
Comparison of PERT and Conventional BICMOS process flow
Standard BICMOS process Additional steps for PERT
Substrate: p-type, 20 ohm-cm
Buried n-layer Implant: As 3100keV,anneal
(Buried layer implant which is not shown)
Epitaxial growth Si: 1

20-nm pad oxide growth+ 200-nm nitride

deposition
550-nm shallow deep trench etch
Channel stop implant: Boron, 4
deep trench etch
Channel stop implant: Boron,
30-nm sacrificial oxide growth and wet etch
Trench fill(30-nm thermal oxide and 1𝜇𝑚
TEOS)
CMP
Cont..
Standard BICMOS Additional steps for PERT
Nitride and pad oxide removal (11% HF)
20-nm gate oxide + 20-nm -Si deposition
Collector plug implant (P, 2) and anneal
N-channel threshold voltage adjust and
antipunchthrough
p-channel threshold voltage adjust and
antipunchthrough
Base implant(2.4)
Collector enhancement implant ()

Oxide removal (single poly npn)

Cont….
Standard BICMOS Additional steps for PERT
Base anneal (90020 minutes)
350-nm poly-1 deposition
1000-ohm resistor implant: B, 3.3, 35keV

Emitter poly implant (As, ) in single poly bipolar

devices
Emitter poly implant (As, 1.5 )in PERT
40-nm nitride deposition
Poly-1 mask-1, Etch poly-1

Etch gate oxide wet chemically

Poly-2 deposition (200nm)
See Figure 2.58a (below)
Poly-2 anisotropic etchback
Cont…
Standard BICMOS Additional Steps for PERT
See Figure 2.58b(below)
Poly-etch and reoxidation (900 minutes)
LDD nMOS
LDD pMOS ( B, 2.4)– also linkup bipolar oxide
spacer formation
60-nm poly-3 strap deposition and patterning

Source/drain (base and collector contacts)

Implants and anneal (900 minutes)
Salicidation TiSi2 (excluding resistors)
Oxide deposition and planarization
W-plugged contacts
AlCu deposition and patterning
Cont….
Standard BICMOS Additional steps for PERT
See Figure 2.58c (below)
Internal planarization
W-plugged Vias
AlCu deposition and patterning
passivation

Planarization- creating a planar surface which is suitable to carry the further

fabrication steps
CMP– chemical mechanical planarization: It is a step which is used multiple times at
each layer of the wafer to remove excess materials
Wet etch- Etching by use of chemicals
Dry and isotropic etch-Etching by use of plasma and used for an perfect vertical side
wall etch
FIG 2.58: Process flow for formation of PERT, a single-poly npn
transistor and a pMOS transistor
• Two poly masks are needed for the fabrication of the PERT (see Fig
2.58 a,b)
• The first poly mask defines the poly rim against which the poly
emitter ridge will lean
• A 200-nm thick polysilicon layer(poly-2) is then deposited and etched
back
• This poly-2 layer is later removed entirely from the wafer surface
except for the regions around ridges where the PERT active areas are
present
• The second poly-1 mask defines the MOS gates, emitter of the PERT
and the conventional single-poly devices
• With two poly masks, widening of the gates areas due to the poly
ridges are avoided
• (FROM FIG 2.58c) the strap connections to the active areas are achieved by
means of deposition of the polysilicon layer
• After the implantation and annealing steps, the silicidation process converts
the polysilicon into silicide
• The Straps plays a dual role of functioning as interconnects and silicides
and also reduces the series resistance of the collector
• The basic BICMOS process require 19 mask steps
• The end products are CMOS devices, single-poly npn bipolar devices, two
level of metallization, passivation and 1000-ohm/square resistor
• The deep trench, PERT emitter and strap modules requires 3 additional
mask steps
• Total mask required for this process= 19(for basic BICMOS process)+3(for
The deep trench, PERT emitter and strap modules)
Advantages Due to shallow trench isolation
• The advantages of using STI is
1) Reduction of the peripheral contribution to the base collector
capacitance
2) Better definition of active regions with locos, allowing the smaller
dimensions to be achieved without the occurrence of enhanced bird
beak
(When dimensions are smaller then bird beak will occur due to the use
of LOCOS then defining the active areas for this process will gets
difficult So by using Shallow trench isolation the bird beak can be
reduced and active areas can be defined easily)
Thank you