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8051 IO Ports

1. Configure port 1 pins as input and output by writing 1 to port 1 latch 2. Continuously read the input port 1 pins and write to output port 1 pins 3. This will display the switch status on the corresponding LEDs in real-time The program continuously reads the input port 1 pins where the switches are connected and writes the same value to the output port 1 pins where the LEDs are connected. This allows the switch status to be displayed on the LEDs in real-time without any delay.

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0% found this document useful (0 votes)
59 views38 pages

8051 IO Ports

1. Configure port 1 pins as input and output by writing 1 to port 1 latch 2. Continuously read the input port 1 pins and write to output port 1 pins 3. This will display the switch status on the corresponding LEDs in real-time The program continuously reads the input port 1 pins where the switches are connected and writes the same value to the output port 1 pins where the LEDs are connected. This allows the switch status to be displayed on the LEDs in real-time without any delay.

Uploaded by

Deepak
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 38

8051

I/O Ports
8051 I/O Ports
• Every pin have D-latch and port SFR is made up of
these latches (8 latches per port).
• To configure a port as input port write 1 to it.
• To configure a port as port does not require any
special setting. Writing a logic status to latch will
output same at port pin.
• After RESET all the port SFRs contain 1 i.e. they are
ready to be used as input as well as ready to output
Logic 1.

8051 I/O Ports – Manish Tiwari 2


8051 I/O Port 1

• Internal pull up is active FET pull up to increase the response


time.
• Limited current driving capability due to internal pull up.
8051 I/O Ports – Manish Tiwari 3
Writing “1” to Output Pin P1.X

Read latch Vcc


TB2
Load(L1) 2. output pin is
1. write a 1 to the pin Vcc
1 P1.X
Internal CPU D Q
bus P1.X pin
0 output 1
Write to latch Clk Q M1

TB1
Read pin

8051 IC
8051 I/O Ports – Manish Tiwari 4
Writing “0” to Output Pin P1.X

Read latch Vcc


TB2
Load(L1) 2. output pin is
1. write a 0 to the pin ground
0 P1.X
Internal CPU D Q
bus P1.X pin
1 output 0
Write to latch Clk Q M1

TB1
Read pin

8051 IC
8051 I/O Ports – Manish Tiwari 5
Reading “High” at Input Pin

Read latch Vcc 2. MOV A,P1


TB2 external pin=High
1. write a 1 to the pin MOV Load(L1)
P1,#0FFH

1 1 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC

8051 I/O Ports – Manish Tiwari 6


Reading “Low” at Input Pin

Read latch Vcc 2. MOV A,P1


TB2
1. write a 1 to the pin Load(L1) external pin=Low
MOV P1,#0FFH
1 0 P1.X pin
Internal CPU bus D Q
P1.X
0 M1
Write to latch Clk Q

TB1
Read pin
3. Read pin=1 Read latch=0
Write to latch=1
8051 IC

8051 I/O Ports – Manish Tiwari 7


I/O Port 1 contd.
• When Q=1, transistor N is OFF, pin P1.x is connected to
Vcc. Leaving the pin as it is inputs Logic 1.
• To input Logic 0 external devices can drive it to Logic 0.

• To output Logic 1, write D=1, so Q=1, transistor N is OFF,


pin P1.x is connected to Vcc. So the output is Logic 1.
• To output Logic 0, write D=0, so Q=0, transistor N is ON,
pin P1.x is connected to Ground. So the output is Logic 0.

8051 I/O Ports – Manish Tiwari 8


8051 I/O Port 2

• Internal pull up is active FET pull up to increase the response


time.
• Limited current driving capability due to internal pull up.
8051 I/O Ports – Manish Tiwari 9
8051 I/O Port 3

• External Pull ups are not required.


• Internal pull up is active FET pull up to increase the response
time. 10
8051 I/O Ports – Manish Tiwari
I/O Port 2 & 3
• Architecture is similar to that of port 3.
• Both comprises internal FET pull ups.
• Port 2 have additional function of providing higher byte of
address A8-A15.
• Port 3 provides additional signals like external interrupts
(INT0 & INT1) event counter inputs (T0 & T1), serial
communication lines TxD & RxD and the Read & Write
control signals.
• Note that all functions available at multifunction pin can
not be used at the same time, at any port.

8051 I/O Ports – Manish Tiwari 11


8051 I/O Port 0

Control = 0 Switch is connected to Q’. Port 0 Now acts as general Purpose


I/O port.
Control = 1 Switch is connected to Address/Data. Port 0 Now acts as AD0-
AD7 line of 8051 that is to be used to access external memory.
8051 I/O Ports – Manish Tiwari 12
I/O Port 0 contd.
I/O Mode (Control = 0)
• Upper transistor is OFF, so Vcc is prohibited from P0.x.
Lower transistor is connected to Q’.
• When Q=1, lower transistor is OFF, pin P0.x floats.
External devices can drive it to HIGH/LOW for i/p.
• To o/p logic 1, D=1 so Q=1 external pull up is required.

• To o/p logic 0, D=0 so Q=0. Lower transistor turns ON


connecting P0.x to Ground. So O/p is Logic 0.

8051 I/O Ports – Manish Tiwari 13


I/O Port 0 contd.
Address/Data Mode (AD0-AD7) (Control = 1)
• When AD=1 Lower transistor is OFF, Upper transistor is
ON, Vcc is connected to P0.x. O/p = Logic 1.
• When AD=0 Upper transistor is OFF, Lower transistor is
ON, Ground is connected to P0.x. O/p = Logic 0.
• No external pull up is needed when external memory is
connected.
• Generally FAN OUT is 4. Connecting more than 4 external
devices requires external buffers to increase FAN OUT.

8051 I/O Ports – Manish Tiwari 14


8751 Module Pin Description

8051 I/O Ports – Manish Tiwari 15


Operation on Port
READ Operation
• When an I/O Port is source, data read will be performed
from port pin.
e.g. MOV A, P0
Reads the data from port 0 pins and copy to A.
WRITE Operation
• When an I/O Port is destination, data write will be
performed on port latches.
e.g. MOV P1, A
Writes data content of A to port 1 latch.

8051 I/O Ports – Manish Tiwari 16


Operation on Port Contd.
READ-MODIFY-WRITE Operation
• When an I/O Port is both source and destination, then the
data read & write will be on the port latch only. Port pins
are not accessed.
e.g. ORL P2, A
Reads the data from port 2 latches OR it with the A
and store the result back to port 2 latches.
• Why Read-Modify-Write with the Latches only?
Answer is a new question -
– What will be the pin status if latch is written Logic 1
and an NPN transistor is connected to pin?
8051 I/O Ports – Manish Tiwari 17
Program P1

Interface 8 serial switches and 8 LEDs


to 8051 and write a program that
displays status of the switches
continuously on the LEDs.

8051 I/O Ports – Manish Tiwari 18


P1: Figure 1

8051 I/O Ports – Manish Tiwari 19


P1: Figure 2

8051 I/O Ports – Manish Tiwari 20


P1: Figure 3 (Final)

8051 I/O Ports – Manish Tiwari 21


P1: Switches & LEDS
ORG 0000H

START: MOV P1, #0FFH ; Configure P1 as input port.


MOV A, P1 ; Read Switch Status.
MOV P2, A ; Show status through LEDs.
SJMP START ; Do it continuously.

END

8051 I/O Ports – Manish Tiwari 22


Program P2

Interface two 7_Segment display


Digits to 8051 and write an ALP to
display BCD digits stored at memory
location 51H & 52H.

Address Data
51H 02
52H 03

8051 I/O Ports – Manish Tiwari 23


P2: 7-Segment Display

74LS244

8051 I/O Ports – Manish Tiwari 24


P2: 7-Segment Display (Contd.)
DISPLAY1: MOV R7, #02 ; Set Digit counter.
MOV R0, #51 ; Pointer to BCD numbers.
MOV R6, #00 ; Init digital selector.
MOV DPTR, #LOOK_UP ; Pointer to 7-Segment display codes.
BACK1: MOV A, @R0 ; Get BCD to display.
MOVC A, @A+DPTR ; Get display code in A.
MOV P1, A ; Write display code at Port 1.
MOV P3, R6 ; Select display digit.
NOP ; Wait for sometime
NOP
INC R0 ; Address of next BCD.
INC R6 ; Provision to select next digit.
DJNZ R7,BACK1 ; Go back to display next digit
SJMP DISPLAY1 ; Repeat the process.

LOOK_UP DB C0H, F9H, A4H, B0H, 99H, 92H, 82H, F8H, 80H, 90H
8051 I/O Ports – Manish Tiwari 25
Alternate P2: 7-Segment Display

8051 I/O Ports – Manish Tiwari 26


Alternate P2: 7-Segment Display (Contd.)
DISPLAY2: MOV R7, #02 ; Set Digit counter.
MOV R0, #51 ; Pointer to BCD numbers.
MOV R6, #00 ; Init digital selector.
BACK2: MOV A, @R0 ; Get BCD to display.
MOV P1, A ; Write BCD at Port 1.
MOV P3, R6 ; Select display digit.
NOP ; Wait for sometime
NOP
INC R0 ; Address of next BCD.
INC R6 ; Provision to select next digit.
DJNZ R7,BACK2 ; Go back to display next digit
SJMP DISPLAY2 ; Repeat the process.

8051 I/O Ports – Manish Tiwari 27


Program P3

Interface two 7_Segment display


Digits only on Port 1 of 8051 and write
an ALP to display BCD digits stored at
memory location 51H & 52H.

Address Data
51H 02
52H 03

8051 I/O Ports – Manish Tiwari 28


P3: 7-Segment Display

P1.4

8051 I/O Ports – Manish Tiwari 29


P3: 7-Segment Display (Contd.)
DISPLAY3: MOV R7, #02 ; Set Digit counter.
MOV R0, #51 ; Pointer to BCD numbers.
MOV R6, #00 ; Init digital selector.
BACK3: MOV A, R6 ; Get digit selector in A.
SWAP A ; Digit selector at upper nibble (A=00).
ORL A,@R0 ; Get display code at lower nibble of
A (A = 02=Selector : Display Code).
MOV P1, A ; Display BCD number.
NOP ; Wait for sometime
NOP
INC R0 ; Address of next BCD.
INC R6 ; Provision to select next digit.
DJNZ R7,BACK3 ; Go back to display next digit
SJMP DISPLAY3 ; Repeat the process.
8051 I/O Ports – Manish Tiwari 30
Program P4

Interface LCD and write a program to


display ASCII codes stored in memory
from 50H to 54H.

8051 I/O Ports – Manish Tiwari 31


P4: LCD Interface

8051 I/O Ports – Manish Tiwari 32


P4: LCD Interface (Contd.)
Rs Register Select
0: Command Register, 1: Data Register

DB7 BUSY FLAG in Command mode, typical time 20µsec.


BUSY=0 LCD is ready to accept next command or data

E Enable +ve Edge triggering for read operations.


-ve Edge triggering for write operations.

VEE Pot controls the contrast of char. displayed in matrix.


LED Placing a pot can control intensity of back light LCD.

8051 I/O Ports – Manish Tiwari 33


P4: LCD Display (Contd.)
CHECK_BUSY:
; Stay in this routine as long as LCD is BUSY.

CLR P2.0 ; RS=0 Access Command Register .


SETB P2.1 ; R/W’=1 Read Command Register.
SETB P1.7 ; P1.7 as i/p pin since busy flag is at DB7.

BUSY: CLR P2.2 ; E=0


NOP ; Provision for 450 nsec delay.
SETB P2.2 ; E=1 Provide L to H edge for read.
JB P1.7, BUSY ; Keep testing as long as BUSY=1.
RET ; Back to caller.

**E is +ve edge triggered for all read.


8051 I/O Ports – Manish Tiwari 34
P4: LCD Display (Contd.)
LCD_CMD:
; Command word in A. Supply appropriate control and writes
command register of LCD.
LCALL CHECK_BUSY ; Check LCD is available or not.
MOV P1,A ; Write command word at P1.
CLR P2.0 ; Rs=0 Access command register.
CLR P2.1 ; R/W’=0 For write into command register.
SETB P2.2 ; Latch command word at P1 into
NOP Command Register using –ve edge of E.
CLR P2.2
RET ; Back to caller.

8051 I/O Ports – Manish Tiwari 35


P4: LCD Display (Contd.)
LCD_DATA:
; Data to be displayed in A. Supplies appropriate controls and
writes the data present in A into LCD.
LCALL CHECK_BUSY ; Check LCD is available or not.
MOV P1,A ; Write command word at P1.
SETB P2.0 ; Rs=1 Access data register.
CLR P2.1 ; R/W’=0 For write into command register.
SETB P2.2 ; Latch the data at P1 into LCD.
NOP using –ve edge of E.
CLR P2.2
RET ; Back to caller.
8051 I/O Ports – Manish Tiwari 36
P4: LCD Display (Contd.)
LCD_DISPLAY:
; First initializes the LCD and then writes ASCII codes to be
displayed on LCD.
;Initialize LCD
MOV A,#38H ; Init LCD 2 lines 5x7 matrix.
LCALL LCD_CMD ; Write command to LCD.
MOV A,#0EH ; Command to LCD on ,cursor on.
LCALL LCD_CMD ; Write command to LCD.
MOV A,#01 ; Clear LCD command i.e. clear any
LCALL LCD_CMD previous data in data registers.

8051 I/O Ports – Manish Tiwari 37


P4: LCD Display (Contd.)
;Write ASCII codes to be displayed into LCD

MOV R0,#50H ; Initialize memory pointer.


MOV R7,#05 ; Initialize counter.
NEXT:
MOV A,@R0 ; Get digit to be displayed.
LCALL LCD_DATA ; Write data to LCD.
INC R0 ; Provision to point next data.
DJNZ R7, NEXT ; Display next data.
RET ;Back to caller.

8051 I/O Ports – Manish Tiwari 38

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