s

ELECTRONICS_V_MP1_CH5_D R MEHTA
1
9820727071
 The 8051 Oscillator & clock
 Microcontrollers (and many other electrical systems) use crystals
to synchronize operations. The 8051 uses the crystal for precisely
that: to synchronize it’s operation.
 The 8051 operates based on an external crystal. This is an
electrical device which, when energy is applied, emits pulses at a
fixed frequency. One can find crystals of virtually any frequency
depending on the application requirements.
 When using an 8051, the most common crystal frequencies are 12
megahertz and 11.059 megahertz ,with 11.059 being much more
common.
 Why would anyone pick such an odd-ball frequency? There’s a
real reason for it--it has to do with generating baud rates .
 Effectively, the 8051 operates using what are called machine
cycles. A single machine cycle is the minimum amount of time in
which a single 8051 instruction can be
ELECTRONICS_V_MP1_CH5_D executed. Although many
R MEHTA
2
instructions take multiple cycles.9820727071
 The 8051 Oscillator & clock

 The clock frequency, f, establishes the smallest interval of time within the micro-
controller, called the pulse, P. time.
 The machine cycle is itself made up of six states. A state is the basic time interval
for discrete operations of the microcontroller such as fetching an opcode byte,
decoding an opcode, executing an opcode, or writing a data byte.
ELECTRONICS_V_MP1_CH5_D R MEHTA
 Two oscillator pulses define each state. 9820727071
3
 A cycle is, in reality, 12 pulses of the crystal. That is to say, if an
instruction takes one machine cycle to execute, it will take 12 pulses
of the crystal to execute. Since we know the crystal is pulsing
11,059,000 times per second and that one machine cycle is 12 pulses,
we can calculate how many instruction cycles the 8051 can execute
per second: 11,059,000 / 12 = 921,583
This means that the 8051 can execute 921,583 single cycle
instructions per second.
 To calculate the time any particular instruction will take to be
executed, find the number of cycles, C, the instruction takes to
execute.
The time to execute that instruction is then found by multiplying C
by 12 and dividing the product by the crystal frequency:

ELECTRONICS_V_MP1_CH5_D R MEHTA
4
9820727071
e.g.: Find the machine cycle for
(a) XTAL = 11.0592 MHz
(b) XTAL = 16 MHz
Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz;
machine cycle = 1 / 921.6 kHz = 1.085 μs
(b) 16 MHz / 12 = 1.333 MHz;
machine cycle = 1 / 1.333 MHz = 0.75 μs
For example, if the crystal frequency is 16 megahertz, then the
time to execute an ADD A, RI one-cycle instruction is .75
microseconds. A 12 megahertz crystal yields the convenient
time of one microsecond per cycle. An 11.0592 megahertz
crystal, while seemingly an odd value, yields a cycle
frequency of 921.6 kilohertz, which can be divided evenly by
the standard communication baud rates
ELECTRONICS_V_MP1_CH5_D R MEHTAof 19200, 9600, 4800,
5
9820727071
 Program Counter : 16 bit
The Program Counter (PC) is a 2-byte address which tells the 8051
where the next instruction to execute is found in memory. When the
8051 is initialized PC always starts at 0000h and is incremented
each time an instruction is executed.
It is important to note that PC isn’t always incremented by one.
Since some instructions require 2 or 3 bytes the PC will be
incremented by 2 or 3 in these cases.
 The Program Counter is special in that there is no way to directly
modify it’s value(The PC is the only register that does not have
an internal address). That is to say, you can’t do something like
PC=2430h. On the other hand, if you execute LJMP 2340h you’ve
effectively accomplished the same thing.
 Program ROM may be on the chip at addresses 0000h to OFFF h,
external to the chip for addresses that exceed OFFF h, or totally
external for all addresses from 0000h to FFFF h.
ELECTRONICS_V_MP1_CH5_D R MEHTA
6
9820727071
 Data Pointer : 16 bit
The DPTR register is made up of two 8-bit
registers, named DPH and DPL, that are used to
furnish memory addresses for internal and external
code access and external data access. The DPTR is
under the control of program instructions and can
be specified by its 16-bit name, DPTR, or by each
individual byte name, DPH and DPL. DPTR does
not have a single internal address; DPH and DPL
are each assigned an address.

ELECTRONICS_V_MP1_CH5_D R MEHTA
7
9820727071
 Programming Tip:
DPTR is really DPH and DPL taken together as a 16-
bit value. In reality, you almost always have to deal
with DPTR one byte at a time. For example, to push
DPTR onto the stack you must first push DPL and then
DPH. You can't simply plush DPTR onto the stack.
Additionally, there is an instruction to "increment
DPTR." When you execute this instruction, the two
bytes are operated upon as a 16-bit value. However,
there is no instruction that decrements DPTR. If you
wish to decrement the value of DPTR, you must write
your own code to do so.
ELECTRONICS_V_MP1_CH5_D R MEHTA
8
9820727071
MEMORY AND REGISTER ORGANISATION
The 8051 has a separate memory space for code (programs) and
data. We will refer here to on-chip memory and external memory
as shown in figure below. In an actual implementation the
external memory may, in fact, be contained within the
microcomputer chip. However, we will use the definitions of
internal and external memory to be consistent with 8051
instructions which operate on memory(Harvard architecture)

ELECTRONICS_V_MP1_CH5_D R MEHTA
9
9820727071
External Code Memory
The executable program code is stored in this code
memory. The code memory size is limited to
64KBytes (in a standard 8051). The code memory is
read-only in normal operation and is programmed
under special conditions e.g. it is a PROM or a Flash
RAM type of memory.
 
External RAM Data Memory
This is read-write memory and is available for
storage of data. Up to 64KBytes of external RAM
data memory is supported (in a standard 8051).
ELECTRONICS_V_MP1_CH5_D R MEHTA
10
9820727071
Internal Memory
The 8051’s on-chip memory consists of 256
memory bytes organised as follows:

 First 128 bytes:00h to 1F h Register Banks

20h to 2F h Bit Addressable
RAM
30 to 7F h General Purpose
RAM

 Next 128 bytes: 80h to FF h Special Function Registers

ELECTRONICS_V_MP1_CH5_D R MEHTA
11
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
12
9820727071
 The 128-byte internal RAM, which is shown generally in Figure 2.1
and in detail in Figure 2.5, is organized into three distinct areas:
1. 4 Register Banks (32 bytes)
2. bit-addressable area(16 bytes )
3. general-purpose RAM
 Register Banks: 00h to 1Fh
 The 8051 uses 8 general-purpose registers R0 through R7
(R0, R1, R2, R3, R4, R5, R6, and R7). These registers are used in
instructions such as:
ADD A, R2 ; adds the value contained in R2 to the accumulator (1
byte therefore shorter & faster)
 Note since R2 happens to be memory location 02h{only if Register
bank 0 is selected !!!} in the Internal RAM the following instruction
has the same effect as the above instruction => ADD A, 02h (2 byte )
ELECTRONICS_V_MP1_CH5_D R MEHTA
13
9820727071
 Thirty-two bytes from address 00h to 1Fh that make up 32 working
registers organized as four banks of eight registers each. The four
register banks are
 numbered 0 to 3 and are made up of eight registers named RO to R7.
 Each register can be addressed by name (when its bank is selected)
or by its RAM address. Thus R0 of bank 3 is
 R0 (if bank 3 is currently selected)
 or address I8h (whether bank 3 is selected or not).
 Bits RSO and RSI in the PSW determine which bank of registers is
currently in use at any time when the program is running. Register
banks not selected can be used as general-purpose RAM.
 Bank 0 is selected upon reset(by default ).
 Programming Tip: If you only use the first register bank (i.e. bank
0), you may use Internal RAM locations 08h through 1Fh for your
own use. But if you plan to use register banks 1, 2, or 3, be very
careful about using addresses below 20h as you may end up
ELECTRONICS_V_MP1_CH5_D R MEHTA
overwriting the value of your9820727071
"R" registers! 14
 Bit Addressable RAM: 20h to 2Fh (16 bytes/128 bits)
 Total 210 bit addressable locations
-128 byte addressable locations 20h to 2Fh
- Rest SFR (special function registers)
 Individual bits can be manipulated (set ,
cleared,ANDed,ORed etc ) by commands
such as SETB and CLR
 The addresses are accessed as bytes
20h to 2Fh or bits 00h to 7Fh
Thus, if you write the value FFh to
Internal RAM address 20h you’ve
effectively set bits 00h through 07h i.e.
MOV 20h,#0FFh is equivalent to:
SETB 00h , SETB 01h , SETB 02h ,
SETB 03h , SETB 04h , SETB 05h ,
ELECTRONICS_V_MP1_CH5_D R MEHTA
15
SETB 06h , SETB 07h 9820727071
 bit memory isn’t really a new or separate type of memory. It’s just a
subset of Internal RAM. But since the 8051 provides special instructions
to access these 16 bytes of memory on a bit by bit basis it is useful to
think of it as a separate type of memory. However, always keep in mind
that it is just a subset of Internal RAM and that operations performed on
Internal RAM can change the values of the bit variables.
 Programming Tip: If your program does not use bit variables, you may
use Internal RAM locations 20h through 2Fh for your own use. But if you
plan to use bit variables, be very careful about using addresses from 20h
through 2Fh as you may end up overwriting the value of your bits!
 Programming Tip: By default, the 8051 initializes the Stack Pointer (SP)
to 07h when the microcontroller is booted. This means that the stack will
start at address 08h and expand upwards. If you will be using the alternate
register banks (banks 1, 2 or 3) you must initialize the stack pointer to an
address above the highest register bank you will be using, otherwise the
stack will overwrite your alternate register banks. Similarly, if you will be
using bit variables it is usually a good idea to initialize the stack pointer to
some value greater than 2Fh to guarantee that your bit variables are
ELECTRONICS_V_MP1_CH5_D R MEHTA
protected from the stack. 9820727071
16
 Special Function register(SFR)
 SFRs are areas of memory that
control specific functionality of the
8051 processor
 21 SFRs 80 h – FF h
 Some of the registers are both bit
& byte addressable
 Programming Tip: SFRs are used
to control the way the 8051 functions.
Each SFR has a specific purpose and
format. Not all addresses above 80h
are assigned to SFRs. However, this
area may NOT be used as additional
RAM memory even if a given address
hasn’t been assigned to an SFR. Attempting
to use an address that is not defined or empty
ELECTRONICS_V_MP1_CH5_D R MEHTA
17
results in unpredictable results ! 9820727071
 Another view of the same previous diagram: Easier
to memorize the bit addressable SFRs

ELECTRONICS_V_MP1_CH5_D R MEHTA
18
9820727071
 ACC (Accumulator, Addresses E0h, Bit-Addressable):
 Register A & B comprise of the mathematical core of the 8051 CPU
 used for many operations including addition ,subtraction, integer
multiplication ,division & boolean bit manipulations
 Used for all data transfer between 8051 & external memory
 Note that though MOV A,#20h is really the same as MOV E0h, #20h.
However, it is a good idea to use the first method since it only
requires two bytes whereas the second option requires three bytes.

 B (B Register, Addresses F0h, Bit-Addressable):

 The "B" register is used with A register in two instructions: - the
multiply and divide operations.
 The B register is also commonly used by programmers as an auxiliary
register to temporarily store values..

ELECTRONICS_V_MP1_CH5_D R MEHTA
19
9820727071
 PSW (Program Status Word, Addresses D0h, Bit-Addressable):
 Flag : are 1 bit registers provided to store the result of certain
programming instructions
 Other instructions can test the condition of the flags & make decisions
based upon the flag states
 In order that the flags may be conveniently addressed they are grouped
inside the PSW .

ELECTRONICS_V_MP1_CH5_D R MEHTA
20
9820727071
 8051 has 4 math flags that respond automatically to the
outcomes of the math operations :- CY ,AC,OV,P
& 3 general purpose user flags that can be set to 1 or cleared to
0 by the programmer as desired :- F0 ,GF0 & GF1 (last 2 in
PCON)
 Programming Tip: If you write an interrupt handler routine,
it is a very good idea to always save the PSW SFR on the
stack and restore it when your interrupt is complete. Many
8051 instructions modify the bits of PSW. If your interrupt
routine does not guarantee that PSW is the same upon exit as it
was upon entry, your program is bound to behave rather
erratically and unpredictably and it will be tricky to debug
since the behavior will tend not to make any sense.

ELECTRONICS_V_MP1_CH5_D R MEHTA
21
9820727071
 IP (Interrupt Priority, Addresses B8h, Bit-Addressable):
 Interrupt :Is the occurrence of a condition – an event –that causes a
temporary suspension of a program while the condition is serviced by another
program
 The program that deals with an interrupt is called an Interrupt service
routine (ISR) or Interrupt handler
 Need of interrupts :
o To determine the conditions that exist in the internal & external circuits
(apart from using software instructions that jump on the state of the
flags /port pins)
o Real time programming
 An interrupt may either be of low (0) priority or high (1) priority.
 An interrupt may only interrupt interrupts of lower priority. E.g., if we
configure the 8051 so that all interrupts are of low priority except the serial
interrupt, the serial interrupt will always be able to interrupt the system,
even if another interrupt is currently executing. However, if a serial
interrupt is executing no other interrupt will be able to interrupt the serial
interrupt routine since the serial interrupt routine has the highest priority.
ELECTRONICS_V_MP1_CH5_D R MEHTA
22
9820727071
Processing Interrupts

ELECTRONICS_V_MP1_CH5_D R MEHTA
23
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
24
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
25
9820727071
 Timer Flag interrupt :
A
a

 Generated whenever timer roll over from all 1’s to all 0’s.

 Serial port interrupt :

 If a data byte is received from external circuit to serial buffer (SBUF)
register, an interrupt bit , RI, is set to 1 in the SCON register.
 when data byte has been transmitted from serial buffer to outside
circuit, an interrupt bit TI, is set to 1 in the SCON register.

 Serial port interrupt

 Note that these bits aren’t cleared when the interrupt generated program call is
made by the processor . The program that handles serial data communication
MUST reset the RI or TI to 0 to enable the next data communication operation.

ELECTRONICS_V_MP1_CH5_D R MEHTA
26
9820727071
 External interrupt :
 Pins INT0 & INT01 :Allow external
hardware devices to request interrupts
and thus some sort of service from the
8051.
 The external interrupts on the 8051 are
caused (IEx flags are set )by either a
low logic level on the interrupt pin
(P3.2 for interrupt 0 and P3.3 for
interrupt 1) or by a high to low level
transition in the interrupt pin.
 The mode of the interrupt (level
triggered or edge triggered) is selected by altering the ITx(interrupt
type) bit corresponding to the interrupt in the TCON
(Timer CONtrol) register. Both are level triggered on reset .
ELECTRONICS_V_MP1_CH5_D R MEHTA
9820727071
27
 In level mode, the interrupt will be fired any time the processor
samples the input signal and sees a 0.
 For the low to be detected, it must be held for at least one processor
cycle (or 12 oscillator cycles) since the processor samples the input
signal once every instruction cycle.
 In edge mode, the interrupt is fired when a one to zero transition is
detected during back to back samples. Therefore, the zero state of
the input must be held for at least one processor cycle to ensure that
it is sampled. ELECTRONICS_V_MP1_CH5_D R MEHTA
28
9820727071
 Interrupt Latency :
 The 8051 samples the interrupt flags once every processor cycle to
determine if any interrupts are pending.
 An interrupt is requested by the appropriate signal being set for the
processor core to recognize in its next sampling period. Thus, the time
between an interrupt being requested and recognized by the processor is
one instruction cycle. At this point, the hardware will generate a call to
the interrupt service routine in the vector which takes two cycles. Thus,
the overall process takes three cycles total.
 Under ideal conditions (where nothing is blocking the interrupt call) and
no instruction is in the works, an interrupt will be responded to in three
instruction cycles. This response time is excellent and provides the user
with very fast response time to system events.
 There will inevitably be times that an interrupt is not responded to
within the three cycles discussed above. The most significant of these is
when an interrupt of equal or higher priority is being serviced. In this
case, the latency to service the pending interrupt depends entirely on the
ELECTRONICS_V_MP1_CH5_D R MEHTA
ISR currently being executed. 9820727071
29
 Another situation in which the latency will be more than three cycles
occurs when the processor is executing a multi-cycle instruction and
detects a pending interrupt during this instruction. The pending
interrupt will not be serviced until the current instruction is completed.
This situation will add a minimum of one cycle to the latency (assuming
that a two cycle instruction such as a MOVX is executing) to a maximum
of three cycles (assuming the interrupt is detected after the first cycle of a
MUL).
 The maximum condition gives a worst case latency of six instruction
cycles (the three cycles due to the architecture itself and the three cycles
due to the completion of the instruction) when the pending interrupt is
not blocked by a currently executing interrupt.
 The final case in which an interrupt will not be vectored to in three cycles
is when the interrupt was recognized during a write to IE, IP, or during a
RETI (return from interrupt) instruction. This prevents very odd real time
conditions from occurring in your system unexpectedly.

ELECTRONICS_V_MP1_CH5_D R MEHTA
30
9820727071
Reset interrupt (Non mask able) Register value (Hex)
 Ultimate interrupt(since the program may not PC  0000
block the action of the voltage on the RST DPTR  0000

pin),non maskable(since no combination of bit in A  00

B  00
any register can stop/mask the reset action).
SP  07
 Reset is an absolute command to jump to PSW  00
program address 0000h and commence running P0-3  FF
from there . PC isn’t stored for later program IP  xxxooooob
resumption like other interrupts IE  oxxooooob
 Whenever high level is applied to the RST pin , TCON  00
TMOD  00
the 8051 enters a reset condition .After the pin
THO  00
brought low , the internal register will have the
TLO  00
values shown in the table.
TH1  00
 NOTE: Internal RAM isn’t changed by a reset. TH0  00
However the states of the internal RAM when SCON  00
power is first applied are random. SBUF  xx
ELECTRONICS_V_MP1_CH5_D R MEHTA PCON 0xxxxxxxb  31
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
32
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
33
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
34
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
35
9820727071
 36
Polling Sequence : External ELECTRONICS_V_MP1_CH5_D
0 ,Timer 0, External 1,Timer 1,serial port ,Timer 2
R MEHTA
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
37
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
38
9820727071
 Data pointer (DPTR) : 16 bit
Used to access external code or Data memory i.e. used to furnish
memory addresses for internal & external code access & external
data access.
Made up of two 8 bit registers DPL (low byte at address 82H) &
DPH (high byte at address 83H). DPTR does not have a single
internal address.DPH & DPL are each assigned on address.
Is under control of program instructions & can be specified by its
16 bit name i.e. DPTR or by each individual byte name DPH &
DPL.

ELECTRONICS_V_MP1_CH5_D R MEHTA
39
9820727071
DPTR, as the name suggests, is used to point to data. It is
used by a number of commands which allow the 8051 to
access external memory. When the 8051 accesses
external memory it will access external memory at the
address indicated by DPTR.
While DPTR is most often used to point to data in
external memory, many programmers often take
advantage of the fact that it’s the only true 16-bit register
available. It is often used to store 2-byte values which
have nothing to do with memory locations.
The 3 instructions write 55H
into external RAM
location 1000H:
ELECTRONICS_V_MP1_CH5_D R MEHTA
40
9820727071
Input/output pins , ports & circuits
 Four I/O ports (P0 - P3)
 Port 0 ： P0 （ P0.0 ～ P0.7 ） Address 80h, Bit-addressable
8 - bit R/W - General Purpose I/O
low order address and data bus for external memory
 Port 1 ： P1 （ P1.0 ～ P1.7 ）
Only 8 – bit R/W – General Purpose I/O
 Port 2 ： P2 （ P2.0 ～ P2.7 ）
8 – bit R/W – General Purpose I/O
high order address for external memory
 Port 3 ： P3 （ P3.0 ～ P3.7 ）
General Purpose I/O
Timers(T0,T1) – ext. int (INT0, INT1) – Serial (TXD,
RXD) – RD,WR
 Each port can be used as input or output (bi-direction)
ELECTRONICS_V_MP1_CH5_D R MEHTA
41
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
42
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
43
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
44
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
45
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
46
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
47
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
48
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
49
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
50
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
51
9820727071
 Hardware Structure of I/O Pin

Read latch Vcc

B2
Internal
Pull-Up
Internal CPU D Q P1.X
bus P1.X pin

Write to latch Clk Q M1

B1
Read pin

ELECTRONICS_V_MP1_CH5_D R MEHTA
52
9820727071
 Hardware Structure of I/O Pin
• Each pin of I/O ports
– Internally connected to CPU bus
– A D latch store the value of this pin
• Write to latch ＝ 1 ： write data into the D latch
– 2 Tri-state buffer ：
• B1: controlled by “Read pin”
– Read pin ＝ 1 ： really read the data present at the pin
• B2: controlled by “Read latch”
– Read latch ＝ 1 ： read value from internal latch

– A transistor M1 gate
• Gate=0: open
• Gate=1: close
ELECTRONICS_V_MP1_CH5_D R MEHTA
53
9820727071
 Writing “1” to Output Pin P1.X

Read latch Vcc

B2
Internal 2. output pin
Pull-Up is Vcc
1. write a 1 to the pin
D Q
1 P1.X
Internal CPU
bus P1.X pin
0 output 1
Write to latch Clk Q M1

B1
Read pin

ELECTRONICS_V_MP1_CH5_D R MEHTA
54
9820727071
 Writing “0” to Output Pin P1.X

Read latch Vcc

B2
Internal 2. output pin
Pull-Up is ground
1. write a 0 to the pin
Internal CPU D Q
0 P1.X
bus P1.X pin
1 M1
output 0
Write to latch Clk Q

B1
Read pin

ELECTRONICS_V_MP1_CH5_D R MEHTA
55
9820727071
 Reading “High” at Input Pin

Read latch Vcc 2. MOV A,P1

B2 external pin=High
1. write a 1 to the pin MOV
Internal
P1,#0FFH
Pull-Up
1 1 P1.X pin
Internal CPU D Q
bus
P1.X
0 M1
Write to latch Clk Q

B1
Read pin
3. Read pin=1 Read
latch=0
ELECTRONICS_V_MP1_CH5_D R MEHTA
56
9820727071
 Reading “Low” at Input Pin

Read latch Vcc 2. MOV A,P1

B2
1. write a 1 to the pin external pin=Low
Internal
MOV P1,#0FFH Pull-Up
1 0 P1.X pin
Internal CPU D Q
bus
P1.X
0 M1
Write to latch Clk Q

B1
Read pin
3. Read pin=1 Read
latch=0
8051 IC
ELECTRONICS_V_MP1_CH5_D R MEHTA
57
9820727071
 Each port has a D type output latch for each pin
The SFR for each port is made up of these 8 latches
which can be addressed at the SFR address for that
port .
 The port latches should not be confused with the
port pins .The data on the latches doesn’t have to
be the same as that on the pins.
The 2 data paths that are used to read the latch or
the pin data use 2 entirely separate buffers.
The top buffer is enabled when the latch data is
read & lower buffer when the pin state is read.
ELECTRONICS_V_MP1_CH5_D R MEHTA
58
9820727071
 The status of each latch may be read from a latch
buffer .
An input buffer is connected directly to each pin ,so
the pin status may be read independently of the
latch state.
 Different opcodes access the latch or the pin state
as appropriate.
Programmable port pins have completely different
alternate functions. The configuration of the control
circuitry between the output latch & the port pin
determines the nature of any particular port function
ELECTRONICS_V_MP1_CH5_D R MEHTA
59
9820727071
 Programming Tip:
While the 8051 has four I/O port (P0, P1, P2,
and P3), if your hardware uses external RAM
or external code memory (i.e., your program is
stored in an external ROM or EPROM chip or
if you are using external RAM chips) you may
not use P0 or P2. This is because the 8051 uses
ports P0 and P2 to address the external
memory. Thus if you are using external RAM
or code memory you may only use ports P1 and
P3 for your own use.
ELECTRONICS_V_MP1_CH5_D R MEHTA
60
9820727071
 Port 0 Structure :
 Operation when used as address bus for external
memory

ELECTRONICS_V_MP1_CH5_D R MEHTA
61
9820727071
 Internal control signals switch the address lines to
the gate of the FETs

ELECTRONICS_V_MP1_CH5_D R MEHTA
62
9820727071
 Internal control signals switch the address lines to
the gate of the FETs :When address bit=0 ,lower
FET ON, upper FET OFF, logic low at pin

ELECTRONICS_V_MP1_CH5_D R MEHTA
63
9820727071
 Internal control signals switch the address lines to
the gate of the FETs :When address bit=1 , upper
FET ON, lower FET OFF, logic low at pin

ELECTRONICS_V_MP1_CH5_D R MEHTA
64
9820727071


Port 0 is different from other I/O ports

ELECTRONICS_V_MP1_CH5_D R MEHTA
65
9820727071
 Port 1 Structure :
No dual functions. Output latch directly connected to
gate of lower FET ,which has a FET circuit labeled
“internal FET pullup” as active pullup load.

ELECTRONICS_V_MP1_CH5_D R MEHTA
66
9820727071
 Read-Change-Write Operation
Example: Complement Value of a pin (CPL P1.5)

Read latch Vcc

B2
1. Read latch=1 Internal
Pull-Up
2. Complement Bit Value
Internal CPU P1.X pin
D Q
bus
P1.X
3. Write to latch=1
Write to latch Clk Q M1

B1
Read pin

8051 IC
ELECTRONICS_V_MP1_CH5_D R MEHTA
67
9820727071
 Port 2 Structure :
a

ELECTRONICS_V_MP1_CH5_D R MEHTA
68
9820727071
 Port 3

ELECTRONICS_V_MP1_CH5_D R MEHTA
69
9820727071
Port3 Alternate IO

ELECTRONICS_V_MP1_CH5_D R MEHTA
70
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
71
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
72
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
73
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
74
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
75
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
76
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
77
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
78
9820727071
ELECTRONICS_V_MP1_CH5_D R MEHTA
79
9820727071