SHRI MADHWA VADIRAJA INSTITUTE OF

TECHNOLOGY AND MANAGEMENT

Microcontroller
18EC46

Venugopala Rao A S
Dept. of CSE
venugopalrao.cs@sode-edu.in
 8051 Architecture
• Block Diagram

07/08/2024 18EC46 2
 8051 Architecture
• Block Diagram

07/08/2024 18EC46 3
 8051 Architecture
• Block Diagram

07/08/2024 18EC46 4
 8051 Architecture
• Salient features of 8051 microcontroller:
• Eight bit CPU
• On chip clock oscillator
• 4 Kbytes of code memory [ROM] and 128 bytes of data memory [RAM]
• 64 Kbytes of external program memory address space.
• 64 Kbytes of external data memory address space.
• 32 bit directional I/O lines
• can be used as four 8 bit ports or 32 individually addressable I/O lines
• Two 16 Bit Timer/Counter :T0, T1
• Full Duplex serial data receiver/transmitter
• Four Register banks with 8 registers in each bank
07/08/2024 18EC46 5
 8051 Architecture
• Sixteen bit Program counter (PC) and a data pointer (DPTR)
• 8 Bit Program Status Word (PSW)
• 8 Bit Stack Pointer
• Five vector interrupt structure (RESET not considered as an interrupt.)
• 8051 CPU consists of 8 bit ALU with associated registers like accumulator ‘A’, B
register, PSW, SP, 16 bit program counter, stack pointer.
• ALU can perform arithmetic and logic functions on 8 bit variables.
• 8051 has 128 bytes of internal RAM which is divided into
• Working registers [00 – 1F]
• Bit addressable memory area [20 – 2F]
• General purpose memory area (Scratch pad memory) [30-7F]
07/08/2024 18EC46 6
 8051 Architecture
• 8051 has 4 K Bytes of internal ROM. (Address space - 0000 to 0FFFh).
• If the program size is more than 4 K Bytes, 8051 will fetch the code automatically
from external memory.
• Accumulator is an 8 bit register widely used for all arithmetic and logical
operations.
• Accumulator is also used to transfer data between external memory.
• B register is used along with Accumulator for multiplication and division.
• A and B registers together is also called MATH registers.
• PSW (Program Status Word) – An 8 bit register which contains the arithmetic
status of ALU and the bank select bits of register banks.

07/08/2024 18EC46 7
 8051 Architecture
• The heart of the 8051 is the circuitry that generates the clock pulses by which
all internal operations are synchronized.
• Pins XTALI and XTAL2 are provided for connecting a resonant network to form
an oscillator.
• The 8051 requires an external oscillator circuit.
• The oscillator circuit runs around 12MHz.
• The crystal generates 12M pulses in one second.
• The pulse is used to synchronize the system operation in a controlled pace.

07/08/2024 18EC46 8
 8051 Architecture
• Typically, a quartz crystal and capacitors are employed, as shown in Figure.

• A machine cycle is minimum amount time a simplest machine instruction must take.
• An 8051 machine cycle consists of 12 crystal pulses (ticks).
• Instruction with a memory operand needs multiple memory accesses (machine
cycles).
07/08/2024 18EC46 9
 8051 Architecture
• Programming Model:

07/08/2024 18EC46 10
 8051 Architecture
• Closer view:

07/08/2024 18EC46 11
 8051 Architecture

07/08/2024 18EC46 12
 8051 Architecture

• The programming model of the 8051 shows the 8051 as collection of 8- and 16-bit
registers and 8-bit memory locations.
• These registers and memory locations can be made to operate using the software
instructions.
• Most of the registers have a specific function such as A or THO or PC.
• Others, which are generally indistinguishable from each other, are grouped in a
larger block, such as internal ROM or RAM memory.
• Each register, (except program counter), has an internal 1-byte address assigned to
it.

07/08/2024 18EC46 13
 8051 Architecture
• Some registers (marked with an asterisk*) are both byte and bit addressable.
• That is, the entire byte of data at such register addresses may be read or altered, or
individual bits may be read or altered.
• Software instructions are generally able to specify a register by its address, its
symbolic name, or both.
• W.k.t. many of the pins are used for more than one function.
• Programming instructions or physical pin connections determine the use of any
multifunction pins.
• E.g.: P3.0 may be used as a general-purpose 1/O pin, or as an input (RXD) to SBUF,
the serial data receiver register.
• The designer decides which of these two functions is to be used and designs the
07/08/2024 18EC46 14
 8051 Architecture
• Internal RAM organization
• Working Registers
• Register Banks: 00H to 1FH. ( 32 Bytes)

• The 8051 uses 8 general-purpose registers R0 through R7.

• There are four such register banks.
• Selection of register bank can be done through RS1,RS0 bits of
PSW.
• On reset, the default Register Bank 0 will be selected.

07/08/2024 18EC46 15
 8051 Architecture
• Bit Addressable RAM: 20h to 2Fh . (16 Bytes)
• The 8051 supports a special feature which allows access
to bit variables.
• This is where individual memory bits in Internal RAM
can be set or cleared.
• In all there are 128 bits numbered 00h to 7Fh.
• Being bit variables any one variable can have a value 0 or
1.
• A bit variable can be set with a command such as SETB
and cleared with a command such as CLR.

07/08/2024 18EC46 16
 8051 Architecture
• Example
• SETB 25h ; sets the bit 25h (becomes 1)
• CLR 25h ; clears bit 25h (becomes 0)

• bit 25h is actually bit 5 of Internal RAM location 24h.

• The Bit Addressable area of the RAM is just 16 bytes
of Internal RAM located between 20h and 2Fh.

07/08/2024 18EC46 17
 8051 Architecture
• General Purpose RAM: 30h to 7Fh. (80 Bytes)
• Even if 80 bytes of Internal RAM memory are available for general-purpose data
storage, user should take care while using the memory location from 00 -2Fh since
these locations are also the default register space, stack space, and bit addressable
space.
• It is a good practice to use general purpose memory from 30 – 7Fh.
• The general purpose RAM can be accessed using direct or indirect addressing
modes.

07/08/2024 18EC46 18
 8051 Architecture
• Storage Registers in 8051
• We will discuss the following types of storage registers here −
• Accumulator
• R register
• B register
• Data Pointer (DPTR)
• Program Counter (PC)
• Stack Pointer (SP)
• Accumulator
• The accumulator, register A, is used for all arithmetic and logic operations.
• If the accumulator is not present, then every result of each calculation (addition,
multiplication, shift, etc.) is to be stored into the main memory.
07/08/2024 18EC46 19
 8051 Architecture
• The "B" Register
• The "B" register is very similar to the Accumulator in the sense that it may hold an
8-bit (1-byte) value.
• The "B" register is used only by two 8051 instructions: MUL AB and DIV AB.
• To quickly and easily multiply or divide A by another number, we may store the
other number in "B" and make use of these two instructions.
• Apart from using MUL and DIV instructions, the "B" register is often used as yet
another temporary storage register, much like a ninth R register

07/08/2024 18EC46 20
 8051 Architecture
• The "R" Registers
• The "R" registers are a set of eight registers, namely, R0, R1 to R7.
• These registers function as auxiliary or temporary storage registers in many
operations.
• Consider an example of the sum of 10 and 20. Store a variable 10 in an
accumulator and another variable 20 in, say, register R4.
• To process the addition operation, execute the following command −ADD A,R4
• After executing this instruction, the accumulator will contain the value 30.
• Thus "R" registers are very important auxiliary or helper registers.
• The "R" registers are meant for temporarily storage of values

07/08/2024 18EC46 21