PROGRAMMABLE

INTERVAL TIMER
(8253/8254)
INTRODUCTION

• What is a programmable interval timer (8253\54)?

• A device programmed to carry out counter and delay operation for a microprocessor.

• Why use a PIT(8253\54)

• A microprocessor can carry out counter operations by setting one of its registers as a counter and
count pulses coming into its input port.
• It can also carry out delay operations by setting up a register with an initial count.
• The initial count is decremented to 0 after which a pulse is sent as an output.
• In doing so the microprocessor, will use a lot of time in fetching and executing and thus the need
for the PIT(8253\54).
INTRODUCTION (continued)

• 8253\54 is a general purpose, multi-timing element.

• Used as an array of I/O ports in system software.
• It has 3 16-bit counters.
• Each capable of handling different frequencies.
 8Mhz(82C54)
 10Mhz(82C54-10)
 12Mhz(82C54-12)
DIFFERENCE BETWEEN 8253 AND 8254
BLOCK DIAGRAM FOR THE 8253\54
PROGRAMMABLE INTERVAL TIMER
FUNCTIONAL BLOCKS OF 8253\54

• Data bus buffer

A tristate, bidirectional, 8-bit buffer.
Interfaces 8284 with the system data bus.
Externally connected to a demultiplexed data bus.
Read/Write control signals determine direction of data.
FUNCTIONAL BLOCKS OF 8253\54 (continued)

• Read/write logic
Accepts input from system bus.
Generates logic for the other functional blocks.
A1,A0 selects counters or control word register.
Low on RD` indicates to 8354 that microprocessor is performing a read.
A low on WR` indicates CPU is writing control word or initial count.
FUNCTIONAL BLOCKS OF 8253\54 (continued)

• Control word/register
Selected when A1 and A0 are both high(1).
Used in defining counter operation during write.
Read operations cannot be done on CWR.
After writing the CWR, it acts as a control word.
FUNCTIONAL BLOCKS OF 8253\54 (continued)

• Counter 1, counter 2, counter 3

 Are identical in operation and fully independent.
 Each counter can operate in different modes.
 They are all decrement registers.
 Each has 2 inputs(CLK and Gate) and 1 output(OUT).
 CLK provides clock to counter
 Gate controls counter operation.
PIN CONFIGURATION OF 8253/54
PIN CONFIGURATION OF 8253/54 (continued)

• D7-D0(data bus)
Bidirectional tri-stated data bus lines.
Connected to system data bus lines.
Count values for the timer is loaded into the registers of the
timer.
Are also used in initializing the timer.
PIN CONFIGURATION OF 8253/54 (continued)

• CS` (Chip select)

Active low input that enables timer IC.
Enables timer to respond to RD` and WR`.
PIN CONFIGURATION OF 8253/54 (continued)

• RD` (Read )
Active low input to timer.
Input is low during microprocessor read operations.
Signal is used to read status and counter values.
PIN CONFIGURATION OF 8253/54 (continued)

• WR` (Write)
Active low input signal.
It is low during write operations.
Used in writing word CWR.
Writes count values for counter registers.
PIN CONFIGURATION OF 8253/54 (continued)

• A0,A1 (Address lines)

 Used in selection of one of the three
counters or the CWR.
 Connected to system address bus
lines.
 Addresses are decided as shown:
PIN CONFIGURATION OF 8253/54 (continued)

• CLK0, CLK1,CLK2(Clock Input )

Are the three inputs to the three independent counters.
These signals are the ones counted by the counters.
PIN CONFIGURATION OF 8253/54 (continued)

• Gate0,Gate1, Gate2(Gate control)

Active high input signals to counters.
Provides external control to the counters.
Functions vary depending on mode of counters.
Basic function is to start and stop counters.
PIN CONFIGURATION OF 8253/54 (continued)

• OUT0,OUT1,OUT2(output)
Output lines of the three counters.
Provides the output from the three counters.
PROGRAMMING THE 8253/54

• It is done when a control word is written and an initial count.

• The control word register is written into when A0,A1 is 11.
• Control word specifies which counter is being written.
• Initial count is then written into the counter.
• Format of initial count is determined by control word used.
• The figure below shows the function of each bit of the CWR:
PROGRAMMING THE 8253/54 (continued)
PROGRAMMING THE 8253/54 (continued)

• Control word register is written when:

• Bit D0 decides the mode for counting i.e BCD/binary.

• Bits D3D2D1 determines the mode of counter.
• RW0 and RW1 decide number of data bytes to load into counter.
• SC0 and SC1 selects counter for initializing.
WRITE OPERATIONS

• There are two conventions to be followed when writing:

 For each counter, control word should be written first before the initial count.
 Count format must be followed by initial count as specified in Control Word.
 LSB only, MSB only OR LSB followed by MSB.

• Provided the conventions are followed any programming sequence is

allowed.
• Counting is affected as described in the mode.
• A new count input follows the programmed count format.
WRITE OPERATIONS (continued)

• During read/write of a two byte count:

 A routine writing to the same counter shouldn’t be executed
Otherwise, data in the counter will be erroneous.
 WRITE OPERATIONS (continued)

• Formats for initializing control register and loading count registers is as shown:
WRITE OPERATIONS (continued)

• The counters needed are the only ones to be initialized.

• The counters to be used will be loaded with only the required value.
• Then the required counter will be initialized
READ OPERATIONS

• The counter applications require the value of the counter in

progress, check the counter and take decisions based on this
value.
• The methods of reading the value of the counter are:
Simple ready operations for the desired counter (8253 and 8254)
Counter latch commands (8253 and 8254)
Read back command (8254)
SIMPLE READ/WRITE OPERATIONS FOR THE
DESIRED COUNTER (8353/8254)

• Selected with the A1 and A0 output.

• Once the counter is selected, the programmer can perform an I/O operation.
• A control signal is issued from the selected counter to perform this operation.
• The CLK input of the selected counter must be inhibited by using either the GATE input
or external logic
• Otherwise, the count may change when read, giving an undefined result.
COUNTER LATCH COMMAND (8353/8254)

• This command is written to the control word register, selected when A1,
A0 – 11.
• Like a control word, the SC1, SC1 bits select one of the three counters
• D5 and D4 distinguish this command from a control word.
COUNTER LATCH COMMAND (8353/8254)
(continued)

• A1, A0 = 11; = 00; = 1; = 0;

• SC1, SCO - Specify counter to be latched

COUNTER LATCH COMMAND (8353/8254)
(continued)

• Counter’s output latch (OL) latch the count when counter latch command is received.
• The count is then held by the CPU until it is read by the CPU or the counter is
reprogrammed.
• The count is then unlatched automatically and the OL return to “following “ the
countering element (CE)
• This allows for reading the contents of the counters “on the fly “ without affecting
counting.
COUNTER LATCH COMMAND (8353/8254)
(continued)

• Read and writes of the same counter must may be interleaved

• For example, if the counter is programmed to fit two-byte counts, the
following sequence is valid.
 Read the least significant byte.
 Write the new least significant byte.
 Read the most significant byte
 Write the new most significant byte
READ BACK COMMAND (ONLY 8254)

• To get a stable count, a counter is latched with a read-back command.

• This command allows the user to check the count value, programmed mode, and current
state of the OUT pin and null count flag of the selected counter(s).
• The command is written into the control word register.
• The command applies to the counters selected by setting their corresponding bits D3, D2,
D1 = 1
READ BACK COMMAND (ONLY 8254)
A1,A0 = 1,1 = 00; = 1; =0
D7 D6 D5 D4 D3 D2 D1 D0
1 1 CNT2 CNT1 CNT0 0

• D5: 0 = Latch count of selected counter(s)

• D4:0 = Latch status of selected counter(S)
• D3:1 = Select counter 2
• D2: 1 = Select counter 1
• D1: 1 Select counter 0
• D0: Reserved for future expansion, must be 0
READ BACK COMMAND FORMAT

• This command may be used to:

 latch multiple counter outputs (OL) by setting the COUNT bit D5 – 0 and
 selecting the desired counter(s).
• Each counter ‘s latched count is held until is read (or the counter is reprogrammed).
• The counter is automatically unlatched when read
• Other counters remain latched until they are read.
• If multiple read-back commands are issued, all but the first are ignored.
READ BACK COMMAND (ONLY 8254) (continued)

• This command may also be used to latch status information by setting STATUS bit D4 - 0.
• Status must be latched to be read.
• The status of the counter is accessed by a read from that counter.
• Bits D5 through D0 contain the counter’s programmed mode as written in the mode control
word.
• D7 contains the current state of the OUT pin, allowing the user to monitor the counter’s
output via software.
READ BACK COMMAND (ONLY 8254) (continued)

• D7: 1 = Out pin is 1

• 0= Out pin is 0
• D6: 1 = Null Count
• 0=Count available for reading
• D4 - D0 = Counter programmed mode
READ BACK COMMAND (ONLY 8254) (continued)

• Null count D6 indicated when last count written to CR has been loaded into CE
• The operation of the null count is as shown below:
OPERATING MODES PIT 8254

• There are six modes of operation for the counters.

• In all modes the counters operate as down counters. They are defined as :
 Mode 0: Interrupt on Terminal Count/ Event counter
 Mode 1: Hardware Re triggerable One-Shot
 Mode 2: Rate Generator
 Mode 3: Square Wave Mode
 Mode 4: Software Triggered Strobe
 Mode 5: Hardware Triggered Strobe (Re triggerable)
MODE 0: INTERRUPT ON TERMINAL COUNT

• Used for event counting

• Output becomes low when the control word is written.
• It remains low until the counter reaches zero.
• OUT then goes high.
• It remains high until a new count/mode 0 Control Word is written into the Counter.
 GATE =1 enables counting
 GATE =0 Disables counting
 Gate has no effect on OUT
MODE 0: INTERRUPT ON TERMINAL COUNT
(continued)
MODE 1: HARDWARE RETRIGGERABLE ONE-
SHOT

• OUT will be initially high.

• OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse, and
remain low until the Counter reaches zero.
• OUT will then go high and remain high until the CLK pulse after the next trigger.
MODE 1: HARDWARE RETRIGGERABLE ONE-
SHOT (continued)

• If a new count is written to the counter during a one shot pulse , the current
one shot is not affected.
• The counter is loaded with the new count and the one shot pulse continues
until the new count expires.
• New counting starts after new trigger pulse.
 MODE 2: RATE GENERATOR

• Functions like a divide-by-N counter and used to generate a Real Time Clock interrupt.
• OUT will initially be high.
• When the initial count N has decremented to 1, OUT goes low for one clock pulse.
• OUT then goes high again, the count N is reloaded, and the process is repeated.
• MODE 2 is periodic. The same sequence is repeated indefinitely.
MODE 2: RATE GENERATOR (continued)

• For an initial count of N, the sequence repeats every N CLK cycle

 Gate =1 Enables counting
 Gate =0 disables counting
MODE 3: SQUARE WAVE MODE

• Typically used for baud rate generation.

• Out will initially be high.
• When half the initial count is expired, OUT goes low for the remainder of the count.
• When count N loaded is even, output remains high for half the count and low for the rest
half of the count.
• When count N loaded is odd, output remains high for (N+1)/2 and low for (N-1)/2
• MODE 3 is periodic. The same sequence is repeated indefinitely.
MODE 3: SQUARE WAVE MODE (continued)

• An initial count of N results in a square wave with a period of N CLK cycles.

 Gate =1 Enables counting
 Gate =0 disables counting
MODE 4: SOFTWARE TRIGGERED STROBE
• OUT will initially be high.
• When the initial count expires, OUT will go low for one CLK pulse and then go high
again.
• The counting sequence is "triggered" by writing the initial count.
• The Counter is loaded on the next CLK pulse following writing a Control Word and
initial count.
• If a new count is written during counting, it will be loaded on the next clock pulse
• Counting will continue from the new count.
 MODE 4: SOFTWARE TRIGGERED STROBE
(continued)

.
MODE 5: HARDWARE TRIGGERED STRODE
(RETRIGGERABLE)
• The initial state of OUT is high.
• Counting is triggered by a rising edge of GATE.
• After the initial count has expired, OUT will go low for one CLK pulse and then go high again.
• The counter will not be loaded until the CLK pulse after a trigger
• This CLK pulse does not decrement the count.
MODE 5: HARDWARE TRIGGERED STRODE
(RETRIGGERABLE) (continued)

• A trigger results in the counter being loaded with the initial count on the next CLK pulse.
• The counting sequence is triggerable, and GATE has no effect on OUT.
• If a trigger occurs after the new count is written but before the current count expires,
• the counter will be loaded with the new count on the next CLK pulse, and counting will
continue from there.
OPERATION COMMON TO ALL MODES

• Resetting the Control Logic

Writing a control word to a counter resets all control logic and sets
OUT to an initial state
No CLK pulses are required for this operation
OPERATION COMMON TO ALL MODES
(continued)

• Gate Input
 In modes 0, 2, 3, and 4, the Gate input is level sensitive and sampled on the rising
edge of CLK
 In modes 1, 2, 3, and 5, the Gate input is rising-edge sensitive and triggers an edge-
sensitive flip-flop in the counter
 The flip-flop is sampled on the next rising edge of CLK and immediately reset
 Modes 2 and 3 have both edge and level sensitivity for the Gate input
OPERATION COMMON TO ALL MODES
(continued)

• Counter Operation
 New counts are loaded and counters are decremented on the falling edge of CLK
 The largest possible initial count is 0, equivalent to 216 for binary counting and 104
for BCD counting
 The counter does not stop when it reaches zero
 Modes 0, 1, 4, and 5 "wrap around" to the highest count (FFFF hex for binary
counting or 9999 for BCD counting) and continue counting
 Modes 2 and 3 are periodic, reloading the initial count and continuing counting from
there.
GATE PIN OPERATION SUMMARY
SYSTEM INTERFACE OF 8353/54
SYSTEM INTERFACE OF 8353/54 (continued)

• The control signal generator produces four control signals: IOR, IOW, MEMR, and
MEMW.
• Two of these signals are connected to the RD and WR signals of 8253/54.
• The RD` and WR` signals of 8253/54 are connected to IOR and IOW signals for mapped
IO.
• MEMR and MEMW signals are used instead of IOR and IOW signals for memory
mapped IO.
• The A1 and A0 are connected to the demultiplexed A2 and AI address lines of the
processor to generate addresses.
SYSTEM INTERFACE OF 8353/54 (continued)

• BHE is used to enable the odd ports (counters/CWR) of 8253/54, while CS` enables the
8253/54 chip.
• The D0-D7 data lines of even 8253/54 are connected to the processor's D0-D7 data bus,
and D8-D15 lines of odd 8253/54.
• CLK, GATE, and OUT signals are connected to peripheral devices.
INTERFACING OF 8253/54 IN IO MAPPED IO
METHOD

• The control signals used are IOR and IOW.

• IOR is connected with RD, and IOW is connected with WR.
• CS signal is connected with address decoding logic.
• The address decoding logic decodes A0-A7 for 8-bit port addresses and A0-A15 for 16-
bit port addresses.
INTERFACING OF 8253/54 IN IO MAPPED IO
METHOD (continued)
The following show two types of address decoding logic.
The chip select signals are 11101 for Figure (a) and 1X11111111101 for Figure (b).
INTERFACING OF 8253/54 IN IO MAPPED IO
METHOD (continued)

• Chip select signal is used along with either A or BHE signals to generate final chip enable
signals for even or odd 8253/54.
• Address of different counters and CWR are determined based on chip select logic, A, A1,
An, or BHE signals.
𝑨𝟕 𝑨𝟔 𝑨𝟓 𝑨𝟒 𝑨𝟑 𝑨𝟐 𝑨𝟏 𝑨𝟎
1 1 1 O 1 0 0 0 E8H FOR COUNTER 0
1 1 1 O 1 0 1 0 EAH FOR COUNTER 1
1 1 1 O 1 1 0 0 ECH FOR COUNTER 2
1 1 1 O 1 1 1 0 EEH FOR CWR

1 1 1 O 1 0 0 1 E9H FOR COUNTER 0

1 1 1 O 1 0 1 1 EBH FOR COUNTER 1
1 1 1 O 1 1 0 1 EDH FOR COUNTER 2
1 1 1 O 1 1 1 1 EFH FOR CWR
INTERFACING OF 8253/54 IN IO MAPPED IO
METHOD (continued)
INTERFACING OF 8253/54 IN MEMORY MAPPED IO
METHOD

• This method uses MEMR and MEMW as control signals instead of IOR and IOW.
• Chip select logic decodes all address lines from A3-A19.
INTERFACING OF 8253/54 IN MEMORY MAPPED IO
METHOD (continued)
• The complete interfacing circuit for memory mapped 10 technique can be illustrated as:
INTERFACING OF 8253/54 IN MEMORY MAPPED IO
METHOD (continued)
On the basis of chip select logic, A_2and A_1 signals the addresses of different counters
and CWR are:
EXAMPLE ON PROGRAMMING 8253/54

• Initializing 8253/54 in mode 1 to read and load lower 8-bits only assuming that 8253/54
is interfaced in memory mapped IO.
• Solution:
• 12H is the control word for 8253 with the counter in mode 1.
• Binary counter 0 is selected.
• Load lower 8-bits only.
• It latches the count and then stores it in register. So that it can be read.
• Let 05H is the lower 8-bit count
EXAMPLE ON PROGRAMMING 8253/54

• Solution:
• Assuming that the addresses of the counters and CWR are even:
3FFE8H Counter 0
3FFEAH Counter 1
3FFECH Counter 2
3FFEEH = CWR
• Also assuming that the content of the DS is 3000 and the corresponding logical addresses
FFE,H. FFEAH, FFECH, and FFEEH
EXAMPLE ON PROGRAMMING 8253/54

• Program:
MOV AL, 12H: Binary counter O, mode 1
MOV [FFEEH] AL: Read/load lower 8-bits
MOV AL, O5H: Lowers 8-bit count
MOV [FFE8H], AL
MOV AL, 02H Binary counter O, mode 1 counter latch
MOV [FFEEH], AL
MOV AL, [FFE8H] : LSB of counter
INT O3H.
REFERENCES

• Mathur, S. (2011). Microprocessor 8086 architecture, programming and interfacing. PHI

Learning Private Limited.
• Intel 8253 - programmable interval timer. Tutorials Point. (n.d.).
https://www.tutorialspoint.com/microprocessor/microprocessor_intel_8253_programmabl
e_interval_timer.htm