Lecture 11

Integrated Circuit Design

(Current Mirrors)

Woodward Yang
School of Engineering and Applied Sciences
Harvard University
woody@eecs.harvard.edu

1
 Overview

• Reading
– Sedra & Smith: Chapters 6
• Background
So far, we’ve seen how to design and analyze various
amplifier circuits using MOSFETs and BJTs primarily at the
discrete level. In this lecture, we will see how some design
choices change for integrated circuit designs. For ICs,
current mirror circuits play a vital role and so we will focus
on them.

ES154 - Lecture 11 2
 Integrated Circuits vs. Discrete Circuit Design

• Many advantages to IC design

– Put many different components together onto a single chip
• Resistors, capacitors, diodes, transistors (MOS and BJT)
– Small size with LOTS of components
– Low cost
– Better component matching within a chip
• Absolute component values can still vary quite a bit
• Some disadvantages
– Limited component value ranges
– Design cannot be changed once fabricated
– Limited exposure of internal circuit nodes
– Limited power capabilities

ES154 - Lecture 11 3
 Current Mirrors

• Let’s recap some of the basic current mirrors that

we’ve seen
R1
– How do the BJT and MOSFET current mirrors ILOAD
differ?
ISRC

– What conditions must be met for both forms to Q1 Q2 VLOAD

operate correctly?

– What kind of non-idealities should we watch

for?

R1
ILOAD
– How would you model these current sources for
small-signal analysis? ISRC

M1 M2 VLOAD
• Let’s take a closer look at some MOSFET and BJT
current mirrors.

ES154 - Lecture 11 4
 Output Resistance and Matching

• We have seen that current mirrors are used both as current sources
and active loads. There is a limitation to current matching arising from
the output resistance, ro, of the devices.
• There are some techniques that can be used to increase the effective ro
of a current mirror circuit – utilizing cascoding
• Let’s look at the a couple of commonly used MOS current mirror circuits
– Cascoded current mirror
– High-swing (low-voltage) cascode

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 Review of Simple Current Mirror

• Let’s review the original simple current mirror circuit

• Currents are governed by the following equations:
IREF
IOUT
M1 M2
(W/L)1 (W/L)2
– While VGS1=VGS2=VDS1, VDS2 can be different.
So,

• For equal W/L’s current mismatch occurs due to differences

in VDS and 
– Using longer L’s can reduce 
– Cascoding can make VDS1 ~= VDS2

ES154 - Lecture 11 6
 Cascoded Current Mirror

• Add a cascode device M3 P

– set VB so that VX = VY
– IOUT set by current through M2 IOUT
M3
– M3 buffers VY from variations in V P through a form of IREF VB
feedback relying on the gm of M3
• Analyze with a small-signal model and find R OUT X Y
– Apply a test vtst, calculate itst to find ROUT=vtst/itst M1 M2
(W/L)1 (W/L)2
– notice that vbs3 = v= -vx

ROUT

gm3v gmb3vbs3
v ro3 itst

vtst

vx ro2 vbs3
• Output resistance is significantly increased by the gm3ro3 of M3
(looks like an impedance amplifier)

ES154 - Lecture 11 7
 Biasing Cascode Current Mirror

• How do we bias VB?

– Use another diode to set bias on B
• What is the minimum voltage that P can fall to while
keeping M2 and M3 in saturation? IREF P
IOUT
M0 M3

B
X Y
M1 M2

• Comments:
– To keep both M2 and M3 in saturation, requires
high voltage overhead due to the Vt term
– If VB can be set arbitrarily, then…

ES154 - Lecture 11 8
 High-Swing Cascode

• High-swing cascode b/c it enables large

swing on node P
• Also called low-voltage cascode b/c the
voltage across the current source can drop
to a lower voltage level P
IREF
• Characteristics IOUT
M3
– Set VB so that VX and VY just greater M0

than VGS-Vth for M1 and M2 to be in B

saturation X Y
M1 M2
– M1 and M2 set the currents and V X
and VY are ~equal and so good
current matching can be achieved
despite VP variations VB generator
– VPmin = 2VDSsat

ES154 - Lecture 11 9
 Alternative Biasing Method

• Here is another way to bias the high-swing cascode current source

IREF

M0 P
IOUT
M3
Vt
B
X Y
M1 M2

– Make source follower have very small current to give a Vt drop

• In other words, VGS-Vt ~ 0
– But, VX not guaranteed equal to VY
• worse matching between ISRC and IOUT

ES154 - Lecture 11 10
 Gain Boosting

• Another method for increasing the output resistance of a cascode circuit is to

use gain boosting (model M1 as just an output resistance ro1 for simplicity)

Rout Rout Rout Rout

Vb
Vb M2 Vb M2 A3 M2 M2
M3
Vin M1 ro1 ro1 ro1

Gain Boosting Circuit Regulated Cascode

– For the gain boosted cascode circuit…

– Similarly, with a regulated cascode

ES154 - Lecture 11 11
 Simple BJT Current Mirror

• Using our assumption that VBE  0.7V

R1
ILOAD
ISRC
– If we assume that Q1 and Q2 are identical devices
Q1 Q2

• For these equations to hold, assume VA = inf (no

base-width modulation) and  is large

ES154 - Lecture 11 12
 Advanced BJT Current Mirrors

• VCC
If you need to drive many current sources and/or
base current is appreciable, you can…
R1
– Add a third device where Q_3 supplies the
ILOAD
base current ISRC
Q3
• What is VCE1?
• Widlar current source – to generate small currents Q1 Q2

– Add an emitter resistor

VCC

R1
ILOAD
ISRC
– Need to use more accurate model…
Q1 Q2

RE

ES154 - Lecture 11 13
 BJT Current Source Small-Signal Model

• The small-signal model for a Wildar current source is…

VCC

R1
ILOAD
ISRC gm2vbe2 = 0
ro2
vbe2 = 0 ro2
IB2
Q1 Q2 RE

VBE RE RE

– The dependent current source is fixed (no AC component)

and therefore an open circuit
– The output resistance increases by RE

ES154 - Lecture 11 14
 Load Options for Amplifiers

• For IC designs, there are several options for implementing the

load. Let’s review some of these options…
– Resistor
– Diode (nMOS or pMOS)
– Current source (current mirror)

ES154 - Lecture 11 15