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7 Alternative Forms of Pull-Up

The document discusses alternative pull-up methods for basic inverters including: 1) Load resistance RL which occupies too much area in silicon. 2) nMOS depletion mode transistor pull-up which is always on but has high switching dissipation. 3) nMOS enhancement mode transistor pull-up which cannot reach logic 1 and requires an extra supply rail. 4) Complementary MOS (CMOS) pull-up which has no current flow for logic states and provides full logic levels at the output with less speed differences between p-channel and n-channel devices.

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Rajesh Pyla
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2K views15 pages

7 Alternative Forms of Pull-Up

The document discusses alternative pull-up methods for basic inverters including: 1) Load resistance RL which occupies too much area in silicon. 2) nMOS depletion mode transistor pull-up which is always on but has high switching dissipation. 3) nMOS enhancement mode transistor pull-up which cannot reach logic 1 and requires an extra supply rail. 4) Complementary MOS (CMOS) pull-up which has no current flow for logic states and provides full logic levels at the output with less speed differences between p-channel and n-channel devices.

Uploaded by

Rajesh Pyla
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Alternative Forms of Pull-Up

1) Load Resistance RL

2) nMOS depletion mode transistor Pull-Up

3) nMOS enhancement mode transistor Pull-Up

4) Complementary transistor
1) Load Resistance RL

O
Basic Inverter: Transistor with source connected
to ground and a load resistor connected from the drain
to the positive Supply rail

Output is taken from the drain and control input


connected between gate and ground

Resistors are not easily formed in silicon they


occupy too much area
2) nMOS Depletion mode Transistor Pull - Up

O
• Pull-Up is always on , Vgs = 0; in depletion

• Pull-Down turns on when Vin > Vt

• With no current drawn from outputs, Ids for both


transistors is equal

No
current
Current
flow
• when Vin exceeds Vt

Switching of Output from 1 to 0 begins of pull


down device and the pull up device is non-saturation

• when Vin = Logical 1


Dissipation is high since rail to rail current flows
3) nMOS Enhancement Mode Transistor Pull - Up
• when Vin = 1
Dissipation is high since current flows rail to rail.

• Vout can never reach Vdd (logic 1) (due to effect of


channel).

• Vgg can be derived from a switching source (i.e. one


phase of a clock, so that dissipation can be
significantly reduced)

• If Vgg is higher than Vdd, and extra supply rail is


required
Complimentary Transistor Pull – Up (CMOS)
• No current flow for either logical 1 or logical 0
inputs

• Full logical 1 and 0 levels are presented at the


output

• For devices of similar dimensions the p – channel is


slower than the n – channel device
Region 1: Logic 0 , p on ; n off

Region 5: Logic 1 , p off ; n on

Region 2: Vin > Vtn :

Vdsn large – n in saturation ; Vdsp small – p in resistive

Small current from Vdd to Vss


Region 4: same as 2 except reversed p and n

Region 3: Both transistors are in saturation Large


instantaneous current flows

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