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Jtag & Bscan

JTAG and boundary scan testing allows an external tester to test components on a board. It uses a Test Access Port controller and various instructions to shift test patterns onto components and read responses. Common instructions include EXTEST to shift patterns, IDCODE to read component IDs, and HIGHZ to set pins to high impedance state.

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123 views18 pages

Jtag & Bscan

JTAG and boundary scan testing allows an external tester to test components on a board. It uses a Test Access Port controller and various instructions to shift test patterns onto components and read responses. Common instructions include EXTEST to shift patterns, IDCODE to read component IDs, and HIGHZ to set pins to high impedance state.

Uploaded by

karthikp207
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Overview

JTAG AND BSCAN


Test Access Port (TAP) Controller
Boundary scan
Schematic Diagram of a JTAG enabled
device
SAMPLE INSTRUCITON
PRELOAD INSTRCUTION
EXTEST INSTRUCTION
INTEST INSTRUCTION
 Purpose:
1. Shifts external test patterns onto component
2. External tester shifts component responses out
RUNBIST
 Purpose: Allows you to issue BIST command
to component through JTAG hardware
 Optional instruction
 Lets test logic control state of output pins
1. Can be determined by pin boundary scan
cell
2. Can be forced into high impedance state
 BIST result (success or failure) can be left in
boundary scan cell or internal cell
 Shift out through boundary scan chain
 May leave chip pins in an indeterminate state
(reset required before normal operation
resumes)
IDCODE INSTRUCTION
 Purpose: Connects the component device
identification register serially between TDI and
TDO
 In the Shift-DR TAP controller state
 Allows board-level test controller or external
tester to read out component ID
Device ID Register --JEDEC Code
 MSB  LSB
 31 28  27 12  11 1  0

 Part  Manufacturer  ‘1’


 Version  
Number Identity
 (16 bits)  (11 bits)  (1 bit)
 (4 bits)
HIGHZ Instruction
 Purpose: Puts all component output pin signals
into high-impedance state
 Control chip logic to avoid damage in this mode
 May have to reset component after HIGHZ runs
 Optional instruction
BYPASS Instruction
 Purpose: Bypasses scan chain with 1-bit register
USERCODE Instruction
• Purpose: Intended for user-programmable components
(FPGA’s, EEPROMs, etc.)
– Allows external tester to determine user programming of
component
• Selects the device identification register as serially
connected between TDI and TDO
• User-programmable ID code loaded into device
identification register
– On rising TCK edge
• Switches component test hardware to its system function
• Required when Device ID register included on user-
programmable component
Optional / Required Instructions

Instruction Status
BYPASS Mandatory
CLAMP Optional
EXTEST Mandatory
HIGHZ Optional
IDCODE Optional
INTEST Optional
RUNBIST Optional
SAMPLE / PRELOAD Mandatory
USERCODE Optional

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