Recent Trends in Analog Design and Digital Devices

Volume 3 Issue 2
DOI: [To be assigned]

Design for Testability (DFT) for a Chip with Memory and Logic
Pradyumna S Acharya1*, Sujatha D Badiger2
1
Student, Department of Electronic and Communication Engineering, RV College of
Engineering, Bengaluru, Karnataka, India
2
Assistant Professor, Department of Electronic and Communication Engineering, RV College
of Engineering, Bengaluru, Karnataka, India
*Corresponding Author
E-Mail Id: pradyumnas66@gmail.com

ABSTRACT
Faulty chips will reach customer if IC testing is not performed on the fabricated IC. Simple
types of testing such as functional and structural testing are not feasible in case of a large
circuit. So, Design for Testability (DFT) techniques are needed to be added to the block so
that the testing becomes easier and faster. Memory Built in self-test (MBIST) for memory
testing and scan insertion for sequential circuits are the major DFT techniques commonly
used. DFT insertion is done by using the tool called Tessent shell. After the design is done,
patterns are generated by using the tool which target particular fault type. Patterns are
generated for stuck at and transition faults detection. After the patterns are generated, the
DFT design is verified by simulation using Questasim to check that the expected output is
obtained.

Keywords: Built in self-test, design for testability, launch off shift, launch off capture,
memory testing, scan testing

INTRODUCTION Pseudo-random pattern generator (PRPG),

There is a possibility of manufacturing Multiple input shift register (MISR), and a
defects to occur in the fabrication process BIST controller. BIST can be used at any
of an IC. Verification is done to check level of chip hierarchy since the BIST is
whether the functionality of the design is fully embedded. The scan and logic BIST
as expected. But on the manufacturing techniques provide high quality test for
side, VLSI testing is needed to determine random logic.[4]
if a fabricated chip is free of defects [1].
The main objective of Design for Often memory arrays use more than half of
Testability (DFT) is to increase the test the silicon in an IC. Scan test targets the
coverage and to reduce the time required faults at the memory input-output.
for testing. However, the array of memory cells
(silicon where data is stored) is not tested
Common DFT techniques are Scan chain thoroughly with scan. Instead, certain
testing, Logic Built in self-test (LBIST) sequences of patterns are used to test the
and Memory Built in self-test (MBIST). memories and to make sure that the
Scan testing involves replacing all the common defects within the memory cell
sequential elements (flip flops or array are not present. The test algorithms
latches)[3] with a special device called are regular and can be generated easily
scan cell. Using a Built-in self-test (BIST) using embedded test logic. Therefore, it is
function above the scan architecture allows common procedure to design MBIST in
the complete test system to be located the silicon. In test mode, the MBIST
inside the IC. The components of BIST are controller controls the memory inputs and

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 Recent Trends in Analog Design and Digital Devices
Volume 3 Issue 2
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perform reads and writes using algorithms inputs, „2n‟combinations are possible. In
which are predefined. Single MBIST functional testing, all the „2n‟combinations
controller can parallelly test many should be applied to the circuit and the
memories. Due to the dense arrangement output response should be compared.
of the cell arrays, the probability of a Functional testing is feasible for small
defect is relatively high. Thus, devices circuits but extremely difficult and time
with defects can be identified by the consuming for large circuits. If a circuit
MBIST and a structure called Built is Self has 16 pins, then 216 patterns i.e. 65536
Analysis (BISA) will determine if the patterns need to be generated and applied.
failures can be repaired or not. Then a Finding the output of the circuit for all the
repair operation occurs within the silicon patterns will require many months for a
by redundancy substitution such that the batch of IC. This type of testing is not
memory becomes operational [2]. EDT is a suitable for large circuits. So, fault-model
test model in which the compression based testing is used. The common fault
advantage of BIST and the high fault models used are stuck-at and transition
coverage of deterministic stimuli is fault models. In stuck at fault model, a net
combined. is assumed to be fixed to a particular logic.
In transition fault model, the net takes
The following paper is organized as more time to change from one logic to
follows. Section II explains the common another which affects the functionality of
Design for testability techniques. Section sequential circuits. When patterns are
III contains the brief description of the generated by targeting the fault model at a
proposed work. The simulation results particular net, it is necessary for the net to
obtained are presented in section IV. be easily controllable and observable.
Finally, section V concludes the paper. Controllability of a net indicates the ease
of setting the net to a logic value whereas
DESIGN FOR TESTABILITY observability indicates the ease of
TECHNIQUES observing the logic value of the net at the
Design for Testability (DFT) includes primary output. The value of
design techniques that enhance the controllability and observability are found
testability of a circuit and to make the out from the SCOAP (Scandia
process of IC testing easier and faster. IC Controllability-Observability Analysis
testing is done on the manufactured Program). Lower the value of
semiconductor devices to validate that the controllability and observability, easier it
product hardware contains no is to control and observe. The Design for
manufacturing defects. The process of test techniques aim at having
testing involves the comparison of controllability and observability
response of vectors (patterns) from a good throughout the circuit for the easy testing
circuit with the response of vectors (using of the circuit. Widely used techniques are
the same patterns) from a device under test scanning testing and BIST (Built in Self-
(DUT). Test).

Basics of Testing Scan Chain Testing

The different types of testing are based on A common circuit will contain
how the patterns are generated and how combinational logic along with a lot of
they are compared. The simplest type of sequential elements like flip flop. It is
testing is functional testing. It involves extremely difficult to get a logic value at a
applying all possible combinations for all particular flip flop output by using the
the input pins. For e.g. if a circuit has „n‟ combinational logics. Also, thousands of

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 Recent Trends in Analog Design and Digital Devices
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clock cycles will be necessary to get a architectures allow an ATPG process to

logic value to a flip flop output. These generate efficient, targeted-fault-coverage
problems can be solved by using the scan vectors [5].
chain architecture. The scan test

Fig. 1: D Flip Flop and Scan D Flip Flop.

The idea of scan chain is to convert the D the capture mode may be one or two.
flip flops in the circuit to a scan flip flop. Based on the number of clock cycles in the
A scan flip flop is nothing but a capture mode, there are two methods-
multiplelxor added to the input of the D Launch off shift (one clock pulse) and
flip flop. The select signal is called the Launch off capture (two clock pulses).
scan enable (SE). One input of the Launch off shift is used for stuck at fault
multiplexor is the normal input of the flip detection whereas Launch off capture is
flop and another input is the scan input used for transition fault detection.
(SI). The output of the scan flip flop is
called the scan output (SO). After all the Built in Self-Test
flip flops are converted to scan flip flops, Built in self-test is the architecture which
the scan flip flops are stitched together i.e. is present at the chip level and makes it
the scan output of one flop is connected to very easy for the Automatic Test
the scan in of next flip flop so that the scan Equipment to perform testing of the IC.
flip flops form a chain i.e. shift register. If Pseudorandom pattern generator, Circuit
scan inputs and scan outputs are under test (CUT), Output response
considered, the structure behaves like a compactor, ROM, comparator and
shift register. controller are the components of BIST
architecture. The main component of the
When the SE is low, the circuit performs BIST architecture is the controller. With
its normal functionality. Whereas when the the use of the controller, the job of testing
SE is high, the scan chain behaves as a is made easy for the external Automatic
shift register. The required logic value at a test equipment. From outside, the
flip flop can be got easily and faster by controller receives a start signal only and
shifting it through the scan chain. When the outputs from the controller are the
the SE is high for controlling, the mode is done signal and the pass/fail signal. The
called load. When the SE is low, the mode done signal is used by the controller to
is called capture mode. When the SE again show the completion of testing process.
becomes high for observing, the mode is The controller sends control signals to the
called unload. The number of clock cycles pattern generator when generation of
needed in the load/unload mode will be patterns is needed. There will be
equal to the number of flip flops connected multiplexors at the inputs of the CUT and
in the chain. The number of clock cycles in the select signals of the multiplexors are

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 Recent Trends in Analog Design and Digital Devices
Volume 3 Issue 2
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also controller by the controller. The for the actual output and the comparator
multiplexor allows either the test data or compares this signature with the golden
the functional data to the CUT. The correct signature stored in the ROM. The result of
responses are compacted and stored as testing is “pass” if the signatures match
golden signatures in the ROM. The output and “fail” if the signatures do not match.
response compactor produces the signature

Fig. 2: Pattern Generation and Signature Analysis [6]

The pattern generation may be done by memory array. The controller in MBIST
different methods. All the patterns may be comprises address generator which is
stored in a ROM, programs can be written capable of generating addresses in forward
which generate the pattern, counters can be and backward direction. The testing of
used. But the best and the widely used memory is algorithmic. This is possible
method for pattern generation is the Linear because of the uniform structure of the
feedback shift register (LFSR). The circuit memory. The algorithm will be designed
used as output response compactor is the to target various faults possible in the
Multiple input signature register (MISR). memory.
The design of MISR is same as the LFSR
but the only difference between the two is Embedded Deterministic Test (EDT)
that LFSR doesn‟t have any external Embedded deterministic test (EDT)
inputs whereas external inputs are present accomplishes the combination of ATE and
in the MISR. A simpler version of the MBIST by applying data from the tester to
Multiple input signature register is the guide on-chip hardware in providing
Single input signature register (SISR) patterns to the circuit. The benefits of
which has only one input. BIST and ATE are combined in EDT. By
increasing the number of scan chains,
Based on the usage BIST is classified as pattern length is made shorter and external
LBIST (Logic BIST) and MBIST influence is reduced. These are the benefits
(Memory BIST). The difference between of BIST captured in EDT. The benefits of
the two types is that in LBIST, the CUT ATE taken into EDT are deterministic
consists of scan chains and combinational patterns and reduces chip area. EDT
blocks whereas in MBIST, the CUT is the mainly consists of decompressor and

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 Recent Trends in Analog Design and Digital Devices
Volume 3 Issue 2
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compressor.

Fig. 3: General EDT Hardware. [6]

When all the flip flops are combined in a

single chain, the test time is high. To
reduce the test time, multiple chains can be
used parallelly but the problem with
multiple chains is that additional pins are
required. In order to use multiple chains
without creating any pin overhead, the
decompressor is used and to combine the
multiple chains to a lesser number of pins,
a compressor is used.

Design and Implementation Fig. 4: Design Flow.

The DFT for the chip includes Memory
MBIST Insertion
BIST and scan chain insertion. The tool In DFT insertion using Tessent, the design
used for DFT is Tessent shell. Tessent of Memory BIST is done first. Depending
Shell is a Tool command language (Tcl) on the number of memories, their location
shell environment and design data model and clock domains, the number of MBIST
that provides a unified Tcl command set controllers is decided. The memory blocks
and command naming conventions. can be assigned to any one of the
controllers. The BIST controller will not
Context should be specified soon after
be directly connected to the memory
invoking Tessent shell. The two contexts block. Instead, there will be an interface
are dft and patterns. The context dft is used present in between. The address bus and
for design editing or for IP generation. The data bus are connected to the memory
context pattern is used in pattern through the interface. The sequence of
generation or during retargeting. A data events which a controller needs to perform
base called Tsdb (Tessent Shell database) is specified as steps in the code. The
configuration of the MBIST controller
is needed so that the created designs,
should be specified in the DFT
patterns and fault lists are stored in a specification. The benefit of using Tessent
common area which makes it easier to is that it has Instrument connectivity
access for retargeting to top level. language which performs a checking for

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 Recent Trends in Analog Design and Digital Devices
Volume 3 Issue 2
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proper interconnections after the device. Each OCC controller receives a

controllers, interface and collar. A network scan enable (SE) signal and a unique clock
based on IJTAG is used to provide access signal that is generated from one or more
to the BIST controllers present in the clock generators. Phase lock loops (PLL)
design. The use of IJTAG based network are usually the clock generators. On-chip
makes it easier to have a hierarchical clock controllers are used in chips to
design. That means the DFT insertion for control the clocks in shifting and capturing
core is done first and then easily integrated data in and out of scan chain flip-flops.
to the top level. A test access port (TAP) Based on the SE signal the OCC outputs
controller may be used at the top level. the clock pulses with shift frequency or
with the functional frequency. The pulses
EDT and OCC Design needed during capture mode is also
The second step in Tessent DFT insertion obtained from OCC. Shift registers along
is the design of OCC and EDT. On-chip with simple gate logic will be to generate
clock controllers (OCC) are needed to required number of pulses in the capture
synchronize multiple clock signals on the window.

Fig.5: On Chip Clock Controller. [7]

In Figure 5, the clk_out is from a 2:1 in figure 6. When SE is high the output
mux whose select line is the scan enable of the OCC is the scan clock. The shift
signal (scan_en). PLL is the Phase Lock register along with the end gate is used
Loop i.e. the clock generator. The CGC to generate the two clock pulses in the
is the clock gating circuit which is capture mode for Launch off capture
usually AND gate based logic as shown

Fig. 6: Clock Gating Circuit (CGC).

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 Recent Trends in Analog Design and Digital Devices
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Figure 6 shows the clock gating circuit channels. A single scan chain covering all
where En is the enable signal, Clk is the flip flops will result in large test time. In
clock and Gclk is the gated output clock. If order to reduce that we can use multiple
En is high, we get the clock pulses as it is scan chains so that by running the chains
but if the En is low the output of flip flop parallelly, test time is reduced. But the pin
is low which makes the and gate output number will become a constraint. To work
low. The considerations during EDT with the earlier number of pins, EDT is
design is are: the longest chain length, used.
number of chains, number of input/output

Fig. 7: EDT [8]

Scan Chain Insertion procfile where the numbers of clock cycles

Scan testing mainly involves three basic are specified and the dead cycles are
operations – load, capture and unload. The included so that timing constraints are met.
main signal is Scan enable (SE). Scan For stuck at fault detection, “launch off
enable is a global signal. Scan enable is shift” method is usually used in the capture
also called as test mode. When SE is high, mode which involves one clock pulse in
the data is loaded into the scan chain. The the capture window. Whereas for transition
main thing we should focus is the capture fault detection, “launch off capture”
mode i.e. when the SE is low. The clock method is used which involves two clock
pulses needed are different in load and pulses (at-speed) in the capture window,
capture mode. For that reason, the SE Example: if a slow to fall transition has to
controls the OCC. The configuration of the be detected in an and gate, in the first pulse
design in the load, capture and shift mode both inputs of and gate should be made „1‟
is done through the procfiles. Tool will so that output is „1‟ and in the next pulse,
write out a proc file which can be edited. one input is made low which makes the
The frequency of the test clock can be output „0‟. If the gate is good, then „0‟ will
defined. The configuration of various be propagated to output when unloading
signals is done in the procfile for the whereas if slow to fall transition fault is
different modes by using different there, then the value will be „1‟ when
procedures. For the capture window, a sampling and the same value „1‟ goes to
separate procedure is present inside the the output when unloading.

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 Recent Trends in Analog Design and Digital Devices
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Fig. 8: Launch off Shift and Launch off Capture. [9]

In Figure 8, Launch off shift is seen in (a) specify the configurations during shift and
and Launch off capture is seen in (b). The capture. The procfile will be read while
time period during which the SE signal generating the pattern.
remains low is called as the capture
window. In Launch off capture we can see RESULTS AND DISCUSSION
that the clock frequency is higher in the For the patterns generated, simulation is
capture window i.e at speed and the clock done and waveform is observed in
frequency in the shift is lower. Questasim. The waveform for one scan
Considering Launch off shift for stuck at cell is considered to show Launch off shift
faults and Launch off Capture for and Launch off capture. Figure 9 is the
transition faults, patterns are generated for screenshot taken from the actual waveform
the faults respectively. The patterns which is obtained during the simulation of
generated are stored in the tsdb. As one of the generated pattern for detection
mentioned earlier, procfiles are used to of stuck at fault.

d
ti
te
phi
Fig. 9: Launch off Shift.

Figure 9 is the screenshot taken from the the Figure.5.2, the clock signal is named as
actual waveform which is obtained during phi and the SE signal is “te” i.e test enable.
the simulation of one of the generated It is observed that when the “te” is low, a
pattern for detection of stuck at fault. In single clock pulse is present.

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 Recent Trends in Analog Design and Digital Devices
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ti
te
phi

Fig. 10: Launch off Capture.

Figure 10 is the screenshot taken from the fault detection. Even though the pattern
actual waveform which is obtained during count is much lesser for stuck at, the
the simulation of one of the generated coverage obtained for stuck at is more than
pattern for detection of transition fault. In that of transition. The reason for this is that
the Figure.5.3, the clock signal is named as Launch off shift is used in stuck at
phi and the SE signal is “te” i.e. test detection whereas Launch off capture is
enable. It is observed that when the “te” is used in transition fault detection. Launch
low, two clock pulses are present. These off shift is easier and more deterministic
two pulses will be generated from a OCC. when compared to Launch off capture.
It is observed that the clock frequency is
much higher in capture mode than that in CONCLUSIONS
the shift mode. The reason for high IC testing is an important step in the
frequency in capture window is that the manufacturing of an IC. It is sufficient to
detection of transition fault is through at perform functional verification of the
speed testing i.e. the clock frequency is the design once, but testing has to be done for
functional frequency. each IC produced. The time needed to test
an IC is crucial with respect to the time to
As mentioned earlier, Launch off shift is market of the IC. Functional testing is a
used in stuck at fault detection and Launch simple type of testing which involves all
off capture is used for transition fault combinations of the input and checking the
detection. It is known that better coverage output. Functional testing is simple, but it
is obtained in Launch off shift. Test is time consuming. DFT techniques are
coverage of 99.60% is obtained for stuck used in the design so that testing becomes
at fault detection patterns with a pattern easier and faster. Common DFT
count of 1972. Whereas a test coverage of techniques are MBIST, LBIST, and scan
98.39% is obtained with 3868 patterns in chain testing. A block in a chip will have
case of transition fault detection. memory and logic. So, it is necessary to
design MBIST, scan chains. etc. and verify
Table 1: Summary of Coverage Report. the design by simulating patterns.
FAULT PATTERN TEST
TYPE COUNT COVERAGE The design of DFT circuitries is done
Stuck-at 1972 99.60%
using tool called Tessent shell. A standard
Transition 3868 98.39%
sequence of events is defined for tessent
and it has to be followed for any design.
Table 1 tabulates the summary of the
First the design of MBIST is done and the
coverage report. It is clearly observed
MBIST inserted design is stored in the
much lesser pattern is sufficient in stuck at
TSDB. The MBIST inserted design is read
detection when compared to transition

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 Recent Trends in Analog Design and Digital Devices
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from the TSDB and the EDT is designed. 88-91). IEEE.

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The author Pradyumna S Acharya would clock generation-implementation
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about DFT techniques and Mentor Test in Europe (pp. 56-61). IEEE.
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