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Lec10 Slides Memories

This document discusses memories and arrays in Verilog. It describes multidimensional arrays and how they can be used to model memories. Memories are modeled as read-only memory (ROM) that holds a list of items that can be accessed using an input address. A sample ROM is provided to store student exam marks that can be accessed using a 4-bit student ID address. Code is provided to implement this ROM as a Verilog module along with a test bench to simulate accessing different data values. Finally, a simple model for a random access memory (RAM) is described.

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13 views18 pages

Lec10 Slides Memories

This document discusses memories and arrays in Verilog. It describes multidimensional arrays and how they can be used to model memories. Memories are modeled as read-only memory (ROM) that holds a list of items that can be accessed using an input address. A sample ROM is provided to store student exam marks that can be accessed using a 4-bit student ID address. Code is provided to implement this ROM as a Verilog module along with a test bench to simulate accessing different data values. Finally, a simple model for a random access memory (RAM) is described.

Uploaded by

Abdalrhman juber
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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ENCS3310

Advanced Digital Design

Memories in Verilog
Introduction

 Multidimensional Array
 Memories
Arrays

 An array is
 list of items
 all of same type
 indexed by a number.
Arrays
reg [31:0] x[127:0]; // 128-element array of 32-bit wide reg
wire[15:0] y[ 7:0], z[7:0]; //2 arrays of 16-bit wide wires indexed from 7
reg [ 7:0] mema [255:0]; // 256-entry memory mema of 8-bit registers
reg arrayb [ 7:0][255:0]; // two-dimensional array of one bit register
reg [7:0] arrayc [3:0][1:0]; // two-dimensional array of 8-bit register

Assigning Values to Arrays


 mema = 0; // Illegal syntax - Attempt to write to entire array
 arrayb[1] = 0; // Illegal syntax - Attempt to write to elements [1][255]...[1][0]
 arrayb[1][31:12] = 0; // Illegal syntax - Attempt to write to multiple elements
 mema[1] = 0; // Assigns 0 to the second element of mema
 arrayb[1][0] = 0; // Assigns 0 to the bit referenced by indices [1][0]
 arrayc[0][0]= 8’h3c; //Assign 3c to arrayc[0][0]
Arrays Initial Values
eg [7:0] slaves_inload [3:1] =
8'b10001000, 8'b10101010, 8'b11101101};
Memories
 Read-only memory (ROM):
 Holds list of items
 One item selected by input address
Memory example: exam marks
Student Mark Student Mark
0 72
0 48
1 49
1 31
2 67 2 43
3 53 3 35
4 43 4 2B
5 57 5 39
6 61
In Hex 6 3D
7 37 7 25
8 48 8 30
9 55 9 37
10 79 A 4F
11 51 B 33
12 40 C 28
13 61 D 3D
14 58 E 3A
15 62 F 3E
Memory example: exam marks
Student Mark
0 48
1 31
2 43
3 35
In ROM
4 2B
5 39
6 3D
7 25
8 30
9 37
A 4F
B 33
C 28
D 3D
Input Student-ID (4-bit, or 1 hex digit)
E 3A
Output student mark (8-bit or 2 hex digits) F 3E
Memory example: exam marks
Student Mark
0 48
1 31
2 43
3 35
In ROM
4 2B
5 39
6 3D
6 7 25
8 30
9 37
A 4F
3D B 33
C 28
D 3D
Input Student-ID (4-bit, or 1 hex digit)
E 3A
Output student mark (8-bit or 2 hex digits) F 3E
module for ROM Example
4
rom
address

8 data

module rom(address,data);
input [3:0] address;
output [7:0] data;

endmodule
Setting up ROM data
reg [7:0] mem [0:15] = '{8'h48,8'h31,8'h43, 8'h35,
8'h2B, 8'h39, 8'h3D, 8'h25, 8'h30, 8'h37, 8'h4F,
8'h33, 8'h28, 8'h3D, 8'h3A, 8'h3E};
Reading out selected data item
assign data = mem[address];
Complete Code of the ROM
module rom(address,data);
input [3:0] address;
output [7:0] data;
reg [7:0] mem [0:15] = '{8'h48,8'h31,8'h43, 8'h35,
8'h2B, 8'h39, 8'h3D, 8'h25, 8'h30, 8'h37, 8'h4F,
8'h33, 8'h28, 8'h3D, 8'h3A, 8'h3E};

assign data = mem[address];


endmodule
Test bench for the ROM
module rom_tb; Testrom
reg [3:0] address;
wire [7:0] data; 4
input_address rom
rom rom1(address,data);
address
initial data
8
begin
data_output
address = 4'b0000;
repeat(15)
#10ns address = address+1;
end;
endmodule

Create closed system (no inputs or outputs)


Internally it has reg that attach to input and wire to attach to
output of device being tested
Test bench for the ROM
Test bench for the ROM
Student Mark
0 48
1 31
2 43
3 35
4 2B
5 39
6 3D

 As address is given, 7 25

 Indexed data item appears at output


8 30
9 37
A 4F
B 33
C 28
D 3D
E 3A
F 3E
Simple RAM Model
module ram_single(out_data,address, in_data, we, clk);

output reg [7:0] out_data;


input [7:0] in_data;
input [6:0] address;
input we, clk;
reg [7:0] mem [127:0];

always @(posedge clk)


begin
if (we)
mem[address] <= in_data;
else
out_data <= mem[address];
end
endmodule
Summary
 Memory model
 Arrays

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