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L12 Modeling Memory

This document discusses modeling memory in Verilog. It covers modeling read-only memory using a case statement or array initialization. Read-write memory can be modeled with an array, data input and output ports, and a write enable signal. The data output is the array value at the input address during reads, and the array is updated from the data input during writes. Memory values can also be initialized using $readmem.

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Akshaya Mushini
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28 views19 pages

L12 Modeling Memory

This document discusses modeling memory in Verilog. It covers modeling read-only memory using a case statement or array initialization. Read-write memory can be modeled with an array, data input and output ports, and a write enable signal. The data output is the array value at the input address during reads, and the array is updated from the data input during writes. Memory values can also be initialized using $readmem.

Uploaded by

Akshaya Mushini
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Advanced Digital System Design

(EC6L033)

Verilog
Lecture 12: Modeling Memory
Learning Objectives
• Modeling of

• Read-Only Memory in Verilog

• Read-Write Memory in Verilog

[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]


How to Model Memory?
• Memory is typically included by instantiating a pre-
designed module from a design library.

• Alternatively, we can model memories using two-


dimensional arrays.

• Primarily used for simulation purpose

• Sometime for the synthesis of small-sized memories.

[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]


Read-Only Memory in Verilog
• One of the way is to use a case statement to define the
contents of each location in memory based on the
incoming address.

Behavioural Models of a 4x4 Asynchronous ROM


[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]
Read-Only Memory in Verilog
• A second approach is to declare an array and then
initialize its contents.

[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]


Read-Only Memory in Verilog

Behavioural Models of a 4x4 synchronous ROM


[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]
Read-Only Memory in Verilog

Behavioural Models of a 4x4 synchronous ROM


[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]
$readmem(h|b)

https://timetoexplore.net
[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]
$readmem(h|b)
Four 16-bit data values in hex:

https://timetoexplore.net
[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]
$readmem(h|b)
Sixteen 8-bit data values in hex (mixing spaces and newlines):

https://timetoexplore.net
[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]
$readmem(h|b)
Six 3-bit values in binary:

https://timetoexplore.net
[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]
$readmem(h|b)
Six 16-bit values in hex starting at array position 4:

https://timetoexplore.net
[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]
Read/Write Memory in Verilog
• In a simple read/write memory model, there is an output
port that provides data when reading (data_out) and an
input port that receives data when writing (data_in).

• Within the module, an array signal is declared with


elements of type reg.

• To write to the array, signal assignment are made from


the data_in port to the element within the array
corresponding to the incoming address.

[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]


Read/Write Memory in Verilog

• To read from the array, the data_out port is assigned the


element within the array corresponding to the incoming
address.

• A write enable (WE) signal tells the system when to write


to the array (WE == 1) or when to read from the array
(WE == 0).

[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]


Read/Write Memory in Verilog

Behavioural Model of a 4x4 Asynchronous R/W Memory


[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]
Read/Write Memory in Verilog

Behavioural Model of a 4x4 synchronous R/W Memory


[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]
Read/Write Memory in Verilog

[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]


References
• Chapter 10, Introduction to Logic Circuits & Logic Design
with Verilog by Brock J. LaMeres

• Disclaimer: “I don’t claim the ownership of all the slides,


some of the material is picked up from various publicly
available sources on the internet”.

[30/08/2023, IIT BBS] | [Srinivas Boppu] | [SES] | [EC6L033]


Thank you

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