Fathima
Fathima
This feature is useful any time the CPU cannot keep up with the rate of data
transfer, or where the CPU needs to perform useful work while waiting for a
relatively slow I/O data transfer.
DMA Initialization
In this method, system allows DMA controller to use system bus to transfer one word,
after which it should return back control of bus to CPU.
This method reduces maximum I/O transfer rates
It also reduces interference of DMA controller in CPU memory access
It is completely eliminated by designing DMA interface so that system bus cycles are
stolen only when CPU is not actually using system bus.
This is also called as Transparent DMA
DMA Data Tranfer: Block Diagram
Data Transfer: Block Components
Two control signals are used to request and acknowledge a DMA transfer .
The HOLD signal is a bus request signal which asks the microprocessor to release control
of the buses after the current bus cycle.
The HLDA signal is a bus grant signal which indicates that the microprocessor has indeed
released control of its buses by placing the buses at their high-impedance states.
DREQi (DMA request): Used to request a DMA transfer for a particular DMA channel.
DACKi (DMA channel acknowledge): Acknowledges a channel DMA request from a
device.
DMA Data Transfer
Steps:
1. I/O device asserts DRQ signal.
2.DMA controller sends HOLD signal to CPU
3.CPU sends HLDA back to DMA controller
4.DMA controller give DMA acknowledgment back to I/O.
DMA Data Transfer
DMA allows a peripheral device to read from/write to memory without going through the
CPU
DMA allows for faster processing since the processor can be working on something else
while the peripheral can be populating memory.
Disadvantages of DMA
DMA transfer requires a DMA controller to carry out the operation, hence cost of the
system increases.
Cache Coherence problems.
Cache Coherency