CHAPTER FOUR

COMPUTER ORGANIZATION
 The 80X86 Family of CPU’s


The x86 and x64 architectures refer to the two most widely-
used types of instruction set architectures (ISA)

Created by Intel and AMD.

An ISA specifies the behavior of machine code and defines how
the software controls the CPU.

ISA is the hardware and software interface, defining what the
CPU can do and how.
 What is x86 Architecture?

x86 is a type of ISA for computer processors originally developed by Intel in
1978. The x86 architecture is based on Intel's 8086 (hence the name)
microprocessor and its 8088 variant. At first, it was a 16-bit instruction set for
16-bit processors, and later it grew to 32-bit instruction sets.

The number of bits signifies how much information the CPU can process per
cycle. For example, a 32-bit CPU transfers up to 32 bits of data per clock
cycle.

Due to its capability of running on almost any computer, from laptops, home
PCs, and servers, x86 architecture has become popular among numerous
microprocessor manufacturers.

Today, the term x86 denotes any 32-bit processor capable of running the x86
instruction set.
 What is x64 Architecture?

x64 (short for x86-64) is an instruction set architecture based on x86, extended
to enable 64-bit code. It was first released in 2000, introducing two modes of
operation - the 64-bit mode and the compatibility mode, which allows users to
run 16-bit and 32-bit applications as well.

Since the entire x86 instruction set remains implemented in the x64 one, the
older executables run with practically no performance penalties.

The x64 architecture supports much greater amounts of virtual and physical
memory than the x86 architecture, allowing applications to store large data
amounts in memory. Additionally, x64 expands the number of general-purpose
registers to 16, providing further enhancements and functionality.

The x64 architecture allows the CPU to process 64-bits of data per clock cycle,
much more than the x86 one.
 Features

Each architecture set has features that define it and give it an edge in specific use
cases. The following lists showcase the features of x64 and x86:
x86

It uses complex instruction set computing architecture (CISC).

Complex instructions require multiple cycles to execute.

x86 has more registers available but less memory.

Designed with fewer pipelines, but it can handle complex addresses.

System performance is optimized using the hardware approach - x86 relies on
physical components to compensate for low memory.

Uses software-based DEP (Data Execution Prevention).
 Features continued...

x64

Has 64-bit integer capability with backward compatibility for 32-bit applications..

x64 processes large files by mapping the entire file into the process's address space.

Faster than x86 due to its faster parallel processing, 64-bit memory and data bus, and
larger registers.

Supports simultaneous operation of large files on multiple address spaces.
Additionally, x64 emulates two x86 tasks simultaneously and provides a faster
experience than x86.

Loads instructions more effectively and efficiently.

Uses hardware-backed DEP (Data Execution Prevention).
 Applications

Due to their different features and differences in resource access, speed, and
processing power, each architecture set is used for different purposes:
x86

Many of the world's PCs are still based on x86 operating systems and CPUs.

Used for gaming consoles.

Cloud computing segments still use the x86 architecture.

Older applications and programs usually run on 32-bit architecture.

It is better for emulation.

32-bit is still preferred in audio production due to its compatibility with older audio
equipment.
 applications continued...

x64

An increasing number of PCs use 64-bit CPUs and operating systems
based on the x64 architecture.

All modern mobile processors use the x64 architecture.

It is used to power supercomputers.

Used in video-game consoles.

Virtualization technologies are based on the x64 architecture.

It is better suitable for newer game engines as it is faster and provides
better performance.
 Limitations

While both ISAs have limitations, x64 is a newer, more perfected type of
architecture. Below is a list of limitations of both types of architectures:
x86

It has a limited pool of addressable memory.

The processing speeds are lower compared to x64.

Vendors no longer develop applications for 32-bit operating systems.

Modern CPUs require a 64-bit OS.

All devices on the system (video cards, BIOS, etc.) share the available RAM,
leaving even less memory for the OS and applications.
 limitations continued...

x64

It doesn't natively run on older, legacy devices.

Its high performance and speed usually consume more power.

64-bit drivers are unlikely to become available for older systems
and hardware.

Some 32-bit software isn't fully compatible with 64-bit
architecture.
 Is x86 or x64 Better?

Although both x86 and x64 have advantages, the future doesn't tolerate
limits, which means that x86 will eventually be scarcely used or
completely dropped. Additionally, x64 is much faster, can allocate more
RAM memory, and has parallel processing capabilities via the 64-bit
data bus, making it a better choice between the two architecture types.

When choosing which OS type to install, it is always better to install a
64-bit OS because it can run both 32-bit and 64-bit software. On the
other hand, an x86-based OS runs only 32-bit software.

Overall, x64 is much more capable than x86, utilizing all installed RAM,
providing more hard drive space, faster bus speeds, and overall better
performance.

8086 Microprocessor
 Interrupts in 8086

Interrupt is the method of creating a temporary halt during program execution and allows
peripheral devices to access the microprocessor.

The microprocessor responds to that interrupt with an ISR (Interrupt Service Routine),
which is a short program to instruct the microprocessor on how to handle the interrupt.

When the 8086 is executing a program, it can get interrupted because of one the
following: -
1. Due to an interrupt getting activated. This is called as hardware interrupt.
2. Due to an exceptional happening during an instruction execution, such as division of a
number by zero. This is generally termed as exception or traps
3. Due to the execution of an interrupt instruction like “INT 21H”. This is called a software
interrupt. The action taken by the 8086 is similar for all the three cases, except for minor
differences.
 Interrupts in 8086

An interrupt is a condition that halts the microprocessor temporarily
to work on a different task and then returns to its previous task.

An interrupt is an event or signal that requests the CPU’s attention.

This halt allows peripheral devices to access the microprocessor.
Whenever an interrupt occurs, the processor completes the current
instruction and starts the implementation of an Interrupt Service
Routine (ISR) or Interrupt Handler.

ISR is a program that tells the processor what to do when the
interrupt occurs. After the ISR execution, control returns to the main
routine where it was interrupted
 Interrupt Instructions of
8086
1. DI:
 It means Disable Interrupt.
 It is a 1 byte instruction.
 It does not affect any flags.
 All the interrupts except TRAP are disabled.
2. EI:
 It means Enable Interrupt.
 It is a 1 byte instruction.
 It does not affect any flags.
 All interrupts are enabled.
3. SIM:
 It provides additional masking for RST 7.5, RST 6.5 and RST 5.5
 Has 8 bit data format.
4. RIM:
 The status of pending interrupts can be read from accumulator.
 When RIM is executed, 8 bits data is loaded in accumulator.
 Has 8 bit data format
 Types of Interrupts

In general there are two types of
Interrupts:

Internal (or) Software Interrupts
are generated by a software
instruction and operate similarly to a
jump or branch instruction.

External (or) Hardware Interrupts
are caused by an external hardware
module.
 HARDWARE INTERRUPT

Hardware interrupt is caused by any peripheral device by sending a signal through a specified
pin to the microprocessor.

Hardware interrupts are generated by hardware devices when something unusual happens;
this could be a key-press or a mouse move or any other action.

It can be divided into two
1. Maskable(INTR) 2. Non maskable(NMI)
Maskable Interrupts:

There are some interrupts which can be masked (disabled)or enabled by the processor.
Non-Maskable Interrupts:

There are some interrupts which cannot be masked out or ignored by the processor. These are
associated with high priority tasks which cannot be ignored (like memory parity or bus faults).
 NMI (Non-Maskable Interrupt)


It is a single non-maskable interrupt pin (NMI) having higher priority than the
maskable interrupt request pin (INTR)and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −

Completes the current instruction that is in progress.

Pushes the Flag register values on to the stack.

Pushes the CS (code segment) value and IP (instruction pointer) value of the return
address on to the stack.

IP is loaded from the contents of the word location 00008H.

CS is loaded from the contents of the next word location 0000AH.

Interrupt flag and trap flag are reset to 0.
 INTR

INTR (Interrupt Request): It provides a single interrupt request
and is activated by the I/O port.

The INTR is a maskable interrupt pin. It can be accepted
(enable) or rejected (masked).

The microprocessor enabled the interrupt using set interrupt flag
instruction. It should disable using clear interrupt Flag instruction

This interrupt can be masked or delayed. It is a level-triggered
interrupt. It can receive any interrupt type, so the value of IP and
CS will change on the interrupt type received.
 INTR continued...

These actions are taken by the microprocessor −


First completes the current instruction.

Activates INTA output and receives the interrupt type, say X.

Flag register value, CS value of the return address and IP value of
the return address are pushed on to the stack.

IP value is loaded from the contents of word location X × 4

CS is loaded from the contents of the next word location.

Interrupt flag and trap flag is reset to 0
 SOFTWARE INTERRUPTS

Interrupts are generated by a software instruction and operate similarly to a jump or branch instruction.

 256 interrupts are there


INT n is invoked as software interrupts- n is the type no in the range 0 to 255(00 to FF)


Interrupts are divided into three groups


Type 0 to Type4 (Dedicated Interrupts)

- TYPE 0 interrupt represents division by zero situation.

- TYPE 1 interrupt represents single-step execution during the debugging of a program.

- TYPE 2 interrupt represents non-maskable NMI interrupt.

- TYPE 3 interrupt represents break-point interrupt.

- TYPE 4 interrupt represents overflow interrupt.

 INT- Interrupt instruction with type
number


It is 2-byte instruction. First byte provides the op-code and the second byte
provides the interrupt type number. There are 256 interrupt types under this
group.
Its execution includes the following steps −

Flag register value is pushed on to the stack.

CS value of the return address and IP value of the return address are pushed
on to the stack.

IP is loaded from the contents of the word location ‘type number’ × 4

CS is loaded from the contents of the next word location.

Interrupt Flag and Trap Flag are reset to 0.
 INT 3-Break Point Interrupt
Instruction


It is a 1-byte instruction having op-code is CCH. These instructions are inserted
into the program so that when the processor reaches there, then it stops the
normal execution of program and follows the break-point procedure.
Its execution includes the following steps −

Flag register value is pushed on to the stack.

CS value of the return address and IP value of the return address are pushed
on to the stack.

IP is loaded from the contents of the word location 3×4 = 0000CH

CS is loaded from the contents of the next word location.

Interrupt Flag and Trap Flag are reset to 0
 INTO - Interrupt on overflow
instruction


It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH.
As the name suggests it is a conditional interrupt instruction, i.e. it is active only when the
overflow flag is set to 1 and branches to the interrupt handler whose interrupt type number
is 4. If the overflow flag is reset then, the execution continues to the next instruction.
Its execution includes the following steps −

Flag register values are pushed on to the stack.

CS value of the return address and IP value of the return address are pushed on to the
stack.

IP is loaded from the contents of word location 4×4 = 00010H

CS is loaded from the contents of the next word location.

Interrupt flag and Trap flag are reset to 0
THE END