Ch

College of Electronic Technology

Tripoli

CE223: Microcomputer Systems

Fall 2023/2024

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Chapter 2

Microcomputer System Architecture

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Levels of Machines

 There are a number of levels

in a computer, from the user
level down to the transistor
level.

 Progressing from the top

level downward, the levels
become less abstract as
more of the internal structure
of the computer becomes
visible.

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Software

 Machine Language
 Binary Instructions
 Difficult to decipher and write
 Error-prone
 All programs converted into machine language for
execution

Instruction Hex Mnemonic Description Processor

10000000 80 ADD B Add reg B to Acc Intel 8085
00101000 28 ADD A, R0 Add Reg R0 to Acc Intel 8051
00011011 1B ABA Add Acc A and B Motorola 6811

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Software

 Assembly Language
Machine instructions represented in
mnemonics
One-to-one correspondence
Efficient execution and use of memory
Machine-specific

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Software

 High-Level Languages
BASIC, C, and C++
Written in statements of spoken languages
Machine independent
Easy to write and troubleshoot
Larger memory and less efficient execution

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Hardware Models (Arcithecture)

 Hardware models:
Von Neumann Model.
The System Bus Model.

Harvard Model

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Von Neumann Model

 In Von Neuman computer architectures, both data and

program memory are connected to µP by using the same
data bus.
 µP can`t access both memories at the same time.

Shared data bus

µP
Program Data
memory memory

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The System Bus Model

 A refinement of the von Neumann model, the system bus model

has a CPU (ALU and control), memory, and an input/output unit.
 Communication among components is handled by a shared
pathway called the system bus, which is made up of the data
bus, the address bus, and the control bus.

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Harvard Model

 In Harvard computer architectures there is a separate

program bus and data bus.
 µP can read both an instruction and data from memory at
the same time that makes it faster.

µP Data
Program
memory memory

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Data bus

 The data bus is bi-directional

 data or instruction codes from memory or input/output
are transferred into the microprocessor .
 the result of an operation or computation is sent out
from the microprocessor to the memory or
input/output.
 Depending on the particular microprocessor, the
data bus can handle 8 bit or 16 bit data.

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Data Size

Nibble 4 bit

Byte bit 8

Word bit 16

Long word bit 32

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Address bus

 The address bus is unidirectional, over which

the microprocessor sends an address code to the
memory or input/output.
 The size (width) of the address bus is specified
by the number of bits it can handle.
 The more bits there are in the address bus, the
more memory locations a microprocessor can
access.
 A 16 bit address bus is capable of addressing
65,536 (64K) addresses.

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Control bus

 The control bus is used by the

microprocessor to send out or receive
timing and control signals in order to
coordinate and regulate its operation and
to communicate with other devices, i.e.
memory or input/output.

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Microprocessor clock

 Also called clock rate, the speed at which a

microprocessor executes instructions. Every
computer contains an internal clock that
regulates the rate at which instructions are
executed and synchronizes all the various
computer components.
 The CPU requires a fixed number of clock ticks
(or clock cycles) to execute each instruction. The
faster the clock, the more instructions the CPU
can execute per second. Clock speeds are
expressed in megahertz (MHz) or gigahertz
(GHz).

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Computer Hardware Organization

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Processor (CPU)

 Consists of:
 Arithmetic logic unit (ALU)
 This is a combinational circuit that
performs arithmetic and logic operations.
 Control unit
 This is a state machine that generates
control signals that control the ALU and
memory transfers.
 Registers
 These are storage locations in the CPU
Sometimes there is a special register
called an accumulator that is used for
most instructions.

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Arithmetic and logic unit (ALU)

 The component that performs the arithmetic and logical

operations.
 The most important components in a microprocessor, and
is typically the part of the processor that is designed first.
 Able to perform the basic logical operations (AND, OR),
including the addition operation.
 The inclusion of inverters on the inputs enables the same
ALU hardware to perform the subtraction operation
(adding an inverted operand), and the operations NAND
and NOR.

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Example ALU

 This ALU performs

4 different
operations on two
n-bit inputs, A and
B.
 The operation is
determined by a
two-bit opcode
(generated by the
control unit).

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Example ALU

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Example: ADD

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Example: ADD

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Example: SUB

 We want A-B, or A+(-B)

So we add A to the negative of B.

Recall that to negate a two’s

complement number, you invert all
the bits and add 1.

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Example: SUB

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Control Unit

 The circuitry that controls the flow of

information through the processor, and
coordinates the activities of the other
units within it.
 It is a little state machine that generates
control signals for the ALU and memory.
 The sequence of operations is specified
by machine code (the user’s program).
 Instruction register (IR) holds the
fetched instruction.
 Program counter (PC) holds the address
of next instructions.

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Memory

 Memory is a set of registers.

 A decoder selects a single register, based on the address
value.
 The contents of that register are written to or read out to the
data bus.
 In many computer architectures, IO devices are treated just like
memory (this is called memory mapped IO).

OE : Output Enable
WE : Write Enable

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Memory

 Memories are made up of registers. Each register in the

memory is one memory location. Memory locations are
identified using Addresses.
Control 8x8bit memory
Mem. Read Decoder 1 1 0 1 1 0 0 0
Mem.Write 0 1 1 1 0 1 0 0
1 0 1 0 0 0 1 0
Address 0 0 1 0 1 1 1 0
A0 0 1 1 1 0 0 1 1
1 0 1 1 0 0 1 0
A1
0 1 1 0 0 1 1 0
A2 1 1 0 1 1 0 0 1

Data : D0 D1 D2 D3 D4 D5 D6 D7
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Memory (Read)

8x8bit memory
Decoder
Control
1 1 0 1 1 0 0 0
Mem. Read=1 0 1 1 1 0 1 0 0
Mem.Write=0 1 0 1 0 0 0 1 0
00 10 11 10 11 0
1 01 0
Address
0 1 1 1 0 0 1 1
A0=1
0 1 0 0 1 1 0 1
A1=1
0 1 1 0 0 1 1 0
A2=0
1 1 0 1 1 0 0 1

Data : D0 D1 D2 D3 D4 D5 D6 D7

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Memory (Write)

8x8bit memory
Decoder
Control
1 1 0 1 1 0 0 0
Mem. Read=0 0 1 1 1 0 1 0 0
Mem.Write=1 1 0 1 0 0 0 1 0
0 0 1 0 1 1 1 0
Address
0 1 1 1 0 0 1 1
A0=1
0 1 1 0 0 1 0
A1=0
0 1 1 0 0 1 1 10
A2=1
1 1 0 1 1 0 0 1

0 0 0 1 1 1 0 0
Data : D0 D1 D2 D3 D4 D5 D6 D7

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Memory

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8086 Architecture

 The 8086 can be divided into two parts:

 The Bus Interface Unit (BIU).
 The Execution Unit (EU).

 The BIU fetches instructions, reads and writes

data, and computes the 20-bit address.

 The EU decodes and executes the instructions

using the 16-bit ALU.

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8086 Architecture

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Bus Interface Unit

 The BIU sends out addresses, fetches instructions from

memory, reads data from ports and memory, and writes data
to ports and memory.
 In other words, the BIU handles all transfers of data and
addresses on the buses for the execution unit.

 BIU contains:
 Instruction queue.
 Segment registers.
 Instruction pointer.
 Address adder.

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Bus Interface Unit
Instruction Queue
 While the EU is decoding an instruction or executing an Instruction
which does not require use of the buses. The BIU fetches up to six
instruction bytes for the following instructions. The BlU stores these pre-
fetched bytes in a first-In-first-out register set called a queue.
 When the EU is ready for its next Instruction, it simply reads the
instruction byte(s) for the instruction from the queue in the BIU.
 This is much faster than sending out an address to the system memory
and waiting for memory to send back the next instruction byte or bytes.

6
5
4
3
2
1

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The BIU Registers

 The BIU contains the following registers:

IP - Instruction Pointer.
CS - Code Segment Register.
DS - Data Segment Register.
SS - Stack Segment Register.
ES - Extra Segment Register.

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Segment Registers
Memory Address
= B 1111 1111 1111 1111 1111 Highest Memory FFFFFH
Address

The 8086 BIU sends out 20-bit addresses, so it

can address any of 220 or 1.048.576 bytes Extra Segment 64 KB

(1MByte) in memory.
Four segment registers in the BIU are used
to hold the upper 16 bits of the starting Stack Segment 64 KB
addresses of four memory segment:
1.Extra Segment (ES) register.
2.Stack Segment (SS) register.
Code Segment
3.Code Segment ( CS) register. 64 KB

4.Data Segment (DS) register.

Data Segment
64 KB

CS Register
DS Register
SS Register First Memory Address 00000H
ES Register
= B 0000 0000 0000 0000 0000

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Memory Segments
Memory Address
Highest Memory Address FFFFFH

 Data Segment: a section of memory (up to

64kbyte), used to store data (variables), uses DS 64 KB
Extra Segment
register to hold the upper 16 bits of the starting
addresses (segment base).
 Code Segment: a 64 kbyte of memory, used to
store program code (Instructions), CS register is
used to hold segment base of code segment Stack Segment 64 KB

address.
 Stack Segment: is a section of memory set aside
to store addresses and data while a subprogram
Code Segment
executes, the stack segment register is used to 64 KB

hold segment base of stack segment.

 Extra Segment: an extra space (up to 64kbyte) of
memory to store “extra” additional data, the ES
Data Segment
register to hold the upper 16 bits of the starting 64 KB

addresses of extra segment.

First Memory Address 00000H

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Segment Address Highest Memory

Address
FFFFFH

Top of Extra
7FFFFH
Segment
 The address bus of 8086 is 20 bit
Extra Segment
 The 20 bit physical address (also called real or
absolute address) can be represented by 2 X 16 bit Bottom of Extra
Segment
70000H

numbers (segment base : offset form).

Top of Stack
 The start address of segment (Segment Bottom Segment
5FFFFH

Address) = Segment Register * 10H Stack Segment

EX: Bottom of CS: 348AH*10H=348A0H Bottom of Stack

50000H
Segment
 The last address of segment( Segment Top
Address) = Segment Register * 10H + FFFFH
Top of Code
4489FH
EX: Top of CS: 348AH * 10H + FFFFH = Segment

4489FH Code Segment

Bottom of Code
Segment 348A0H
Address
Generation
Top of Data
2FFFFH
Segment

CS=348AH Data Segment

DS=2000H
SS=5000H Bottom of Data
20000H
Segment
ES=7000H

First Memory
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Address
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Physical Address Generation

 Address taken from segment registers like

CS,DS,ES,SS is shifted left for 4-bit.
 Add offset address value from pointer register like
SI,DI,BP,SP,BX,IP.

Segment register address

1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1

Offset address
1 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1

1 0 1 1 0 1 0 0 0 0 1 0 0 1 0 1 1 0 1 1
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Physical Address Generation
• The BIU has a dedicated adder for determining physical
memory addresses.

Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

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Example 1

• If the data segment starts at location

1000h and a data reference contains
the address 29h where is the actual
data?
2 9

:Offset 1001010000000000

:Segment 00000000000010000000

:Address 01000000000010001001

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Physical Address Generation
 Offset, also called Effective Address, or Logical Address, represent
the offset from location 0 of a given segment, it can range from
0000H to FFFFH
 For each segment, there are default registers are used to calculate
Physical address.

Offset Segment Register Segment

(Segment base)
IP CS register Code
BX, DI, SI DS register Data
BP, SP SS register Stack
DI ES register Extra

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Logical Address

 Logical address is specified as Segment:Offset

 Physical address is obtained by shifting the
segment address 4 bits to the left and adding
the offset address.
 Thus the physical address of the logical address
A4FB:4872 is:
A4FB0
+ 4872
A9822

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Example 2

 Calculate the physical address if the starting

address of data segment is 038Eh and an
instruction references a location with an offset
of 0032H bytes from the start of the data
segment.
 The value in DS register is 038Eh.
 The physical address = DS segment address + offset
= 038E0h + 0032h
= 03912h

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Example 3

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Instruction Pointer (IP)
Effective P.
Memory
Address Address
IP is a 16 bit register
contains the Offset Address FFFFH ?
of the next instruction, the
distance in bytes from the
address given by the
current CS register.

Address 0002H
Generation 0001H ?
0000H ?
CS=3000H
DS
SS
ES
IP =0005H

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Execution Unit

 The execution unit EU tells the BIU where to fetch

instructions or data, decodes and executes instructions.
 Both units operate asynchronously to give the 8086 an
overlapping instruction fetch and execution mechanism
which is called as Pipelining.
 EU contains:
 Control Unit.
 Instruction decoder.
 Arithmetic Logic Unit (ALU).
 Pointer and Index register.
 Flag register.

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EU - Control Unit

 The EU contains a control unit with an Instruction decoder.

 The functions of this unit are:
 Directs internal operations.
 Translates instructions fetched from memory into a series of actions which
the EU carries out.

Control Unit

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EU - ALU

 ALU (arithmetic logic unit) is a device that perform a variety of

arithmetic and logical operations on binary words.
 The EU has a 16-bit ALU which can do some arithmetic and logical
operations (instructions), such as ADD, SUB, AND, OR instructions.
 The operation of ALU is controlled by Control System Unit.

ALU

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The EU Registers
 The EU contains the following 16-bit registers:
 AX - the Accumulator
 BX - the Base Register
 CX - the Count Register
 DX - the Data Register
 SP - the Stack Pointer
 BP - the Base Pointer
 SI - the Source Index Register
 DI - the Destination Register
 Flag Register

 The AX, BX, CX, and DX registers can be considers as two 8-bit registers, a High
byte and a Low byte. These are referred to as general-purpose registers (GPR).
 The advantage of using GPR: Since the data is already In the EU, it can be
accessed much more quickly than it could be accessed in external memory.

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Data Registers

 AX
Accumulator Register
Preferred register to use in arithmetic, logic
and data transfer instructions because it
generates the shortest Machine Language
Code.
Must be used in multiplication and division
operations.
Must also be used in I/O operations.

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Data Registers

 BX
 Base Register.
 Also serves as an address register.
 CX
 Count register.
 Used as a loop counter.
 Used in shift and rotate operations.
 DX
 Data register.
 Used in multiplication and division.
 Also used in I/O operations.

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Pointer Registers

 Contain the offset addresses of memory locations.

 Can also be used in arithmetic and other operations.
 SP: Stack pointer
 Used with SS to access the stack segment
 BP: Base Pointer
 Primarily used to access data on the stack
 Can be used to access data in other segments

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Stack pointer (SP)

 The stack is configured as a data structure that

grows downward from high memory to low
memory.
 At any given time, the SP holds the 16-bit
address of the next free location in the stack.
 The stack acts like any other stack when there is
a subroutine call or on an interrupt. ie. pushing
the return address on a jump, and retrieving it
after the operation is complete to come back to
its original location.

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Index Registers

 SI: Source Index register

 is required for some string operations.
 When string operations are performed, the SI register
points to memory locations in the data segment which
is addressed by the DS register.
 DI: Destination Index register
 is also required for some string operations.
 When string operations are performed, the DI register
points to memory locations in the data segment which
is addressed by the ES register.

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FLAGS

• A 16-bit flag register in the EU contains nine active flags.

• A flag is a flip-flop which indicates some condition produced
by the execution of an instruction or controls certain
operations of the EU.
• Six of the nine flags are Status bits, set or reset by the EU
on the basis of the results of some arithmetic or logic
operation, For example: carry flag will be set to a 1 if the
addition of two numbers produces a carry out .
• Certain 8086 instructions check these flags to determine
which of two alternative actions should be done in
executing the instruction.
• The three remaining flags are Control bits, used to control
certain operations of the processor.

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FLAG Register

Carry flag
Overflow
Direction Parity flag

Interrupt enable Auxiliary flag

are status flags 6 Trap Zero

are control flag 3
Sign

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FLAGS
• CF (carry) set if there was a carry from or borrow to the most significant
bit during last result calculation.

• OF (overflow) set if the result is too large positive number, or is too

small negative number to fit into destination operand .

• DF (direction) if set then string manipulation instructions will auto-

decrement index registers. If cleared then the index registers will be
auto-incremented .

• IF (interrupt) Indicates whether external interrupts are being processed

or ignored. Setting this bit enables maskable interrupts.

• TF (trap) Permits operation of the processor in single step mode

(debug).

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FLAGS
• SF (sign) Contains the resulting sign of an arithmetic operation
(1=negative). In other words it is set if the most significant bit of the
result is set.

• ZF (zero) Indicates when the result of arithmetic or a comparison is

zero. (1=yes).

• AF (auxiliary carry) Contains carry out of bit 3 into bit 4 for specialized
arithmetic (BCD).

• PF (parity) set if parity (the number of "1" bits) in the low-order byte of
the result is even.

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8086 Registers summary
15 0
BIU registers ES Extra Segment
CS Code Segment
SS Stack Segment
DS Data Segment
IP Instruction Pointer

15 8 7 0
EU registers
AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS Flag Register

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References

 References:
 Text Books.
 Microprocessors lecture slides from Eng. Jalal Miladi.

 Readings:
 Douglas Hall, Ch2, pp 28-32.

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