Introduction

to
Computer Architecture

Prepared by:
Ruby Dahiya,PhD
Faculty (IITM)
What is Computer Organization and
Computer Architecture?
• Computer Organization is concerned with the
way hardware components operate and the
way they are connected together to form the
computer system.
• Computer Architecture is concerned with the
structure and behavior of the computer seen
by the user.
 It includes the information, formats, the
instruction set and techniques for addressing
memory. Computer Architecture BCA-203 2
 What is Computer Design?
• Computer design is concerned with
the hardware design of the
computer.
• With the formulated computer
specifications, a designer has to
develop hardware for the system.

Computer Architecture BCA-203 3

 Overview of Unit - 1
• This unit deals with the physical organization
of a particular computer.
• It includes the data flow, the micro operations
and control functions.
• These all can be described symbolically by
means of a hardware description language.
• The pre-requisite to understand all the
concepts of computer architecture is the
better understanding of Digital Electronics.
Computer Architecture BCA-203 4
 Overview (contd…)
• One part of the unit introduces the register
transfer language (RTL).
• This will explain how to introduce the micro-
operations in the symbolic form.
• Here, symbols are defined for arithmetic, logic
and shift micro-operations.
• On the completion of the unit, the student will
be able to design a composite arithmetic logic
shift unit.

Computer Architecture BCA-203 5

 Overview (contd…)
• The other part deals with the organization and
design of a basic digital computer.
• The Register Transfer Language (RTL) is used
to describe the internal operation of the
computer and to specify the requirements for
its design.
• This introduces the set of instructions used by
the basic computer.

Computer Architecture BCA-203 6

 Overview (contd…)
• In short, this unit presents the detailed steps
of the hardware organization and design.
• Going through this unit will make you able to
understand to understand the inner workings
of digital computers.

Computer Architecture BCA-203 7

 Preview of the Unit - 1
• Register transfer
• Micro-operation(Arithmetic, Logical and Shift)
• Bus and Memory Transfer
• Computer Registers
• Computer Instructions
• Timing and Control Unit
• Instruction Cycle
• Types of Instructions (Reg. Ref. , Mem. Ref.
and IO Ref.)
• Interrupt Cycle Computer Architecture BCA-203 8
 Lecture-2

Register Transfer
 Microoperations
• The operations on the data in registers are called
micro operations.
• The functions built into registers are examples of
micro operations
– Shift
– Load
– Clear
– Increment
–…

Computer Architecture BCA- 203 10

 Organization Of A Digital System

• Definition of the (internal) organization of a computer

- Set of registers and their functions

- Micro-operations set

Set of allowable microoperations provided

by the organization of the computer

- Control signals that initiate the sequence of

microoperations (to perform the functions)

Computer Architecture BCA- 203 11

 Register Transfer Level
• Viewing a computer, or any digital system, in
this way is called the register transfer level

• This is because we’re focusing on

– The system’s registers
– The data transformations in them, and
– The data transfers between them.

Computer Architecture BCA- 203 12

 Register Transfer Language
• Rather than specifying a digital system in words, a specific
notation is used, register transfer language
• For any function of the computer, the register transfer
language can be used to describe the (sequence of)
microoperations
• Register transfer language
– A symbolic language
– A convenient tool for describing the internal organization
of digital computers
– Can also be used to facilitate the design process of digital
systems.

Computer Architecture BCA- 203 13

 Designation Of Registers
• Registers are designated by capital letters, sometimes
followed by numbers (e.g., A, R13, IR)
• Often the names indicate function:
– MAR - memory address register
– PC - program counter
– IR - instruction register
• Registers and their contents can be viewed and represented in
various ways
– A register can be viewed as a single entity:
– Registers may also be represented showing the bits of data
they contain

Computer Architecture BCA- 203 14

 Designation Of Registers
• Designation of a register
- a register
- portion of a register
- a bit of a register

• Common ways of drawing the block diagram of a register

Register Showing individual bits

R1 7 6 5 4 3 2 1 0

15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields

Computer Architecture BCA- 203 15

 Register Transfer
• Copying the contents of one register to another is a register
transfer
• A register transfer is indicated as : R1 ← R2

– In this case the contents of register R2 are copied (loaded)

into register R1
– A simultaneous transfer of all bits from the source R2 to
the destination register R1, during one clock pulse
– Note that this is a non-destructive; i.e. the contents of R2
are not altered by copying (loading) them to R1

Computer Architecture BCA- 203 16

 Register Transfer
• A register transfer such as R3  R5 implies that the digital
system has

– the data lines from the source register (R5) to the

destination register (R3)
– Parallel load in the destination register (R3)
– Control lines to perform the action

Computer Architecture BCA- 203 17

 Control Functions
• Often actions need to only occur if a certain condition is true
• This is similar to an “if” statement in a programming language
• In digital systems, this is often done via a control signal,
called a control function
– If the signal is 1, the action takes place
• This is represented as- P: R2 ← R1
Which means “if P = 1, then load the contents of register R1
into register R2”,
i.e., if (P = 1) then (R2  R1)

Computer Architecture BCA- 203 18

 Hardware Implementation Of
Controlled Transfers
Implementation of controlled transfer
P: R2 R1

Block diagram Control P Load

R2 Clock
Circuit
n
R1

t t+1
Timing diagram
Clock

Load
Transfer occurs here

• The same clock controls the circuits that generate the control function
and the destination register
• Registers are assumed to use positive-edge-triggered flip-flops
Computer Architecture BCA- 203 19
 Simultaneous Operations
• If two or more operations are to occur
simultaneously, they are separated with
commas

P: R3  R5, MAR  IR

• Here, if the control function P = 1, load the

contents of R5 into R3, and at the same time
(clock), load the contents of register IR into
register MAR
Computer Architecture BCA- 203 20
 Basic Symbols For Register Transfers

Symbols Description Examples

Capital letters Denotes a register MAR, R2
& numerals
Parentheses () Denotes a part of a register R2(0-7), R2(L)

Arrow  Denotes transfer of information R2  R1

Colon : Denotes termination of control function P:
Comma , Separates two micro-operations A  B, B  A

Computer Architecture BCA- 203 21

 Connecting Registers
• In a digital system with many registers, it is impractical to
have data and control lines to directly allow each register to
be loaded with the contents of every possible other registers
• To completely connect n registers  n(n-1) lines
• O(n2) cost
– This is not a realistic approach to use in a large digital
system
• Instead, take a different approach i.e., have one centralized
set of circuits for data transfer – bus
• Have control circuits to select which register is the source,
and which is the destination

Computer Architecture BCA- 203 22

 Summary Of Register Transfer
Microoperations
A B Transfer content of reg. B into reg. A
AR DR(AD) Transfer content of AD portion of reg. DR into reg. AR
A  constant Transfer a binary constant into reg. A
ABUS  R1, Transfer content of R1 into bus A and, at the same time,
R2 ABUS transfer content of bus A into R2
AR Address register
DR Data register
M[R] Memory word specified by reg. R
M Equivalent to M[AR]
DR  M Memory read operation: transfers content of
memory word specified by AR into DR
M  DR Memory write operation: transfers content of
DR into memory word specified by AR

Computer Architecture BCA- 203 23

 Lecture-3

Bus and Memory Transfer

 Bus And Bus Transfer
Bus is a path (of a group of wires) over which information
is transferred, from any of several sources to any of several
destinations.
From a register to bus: BUS  R

Register A Register B Register C Register D

Bus lines

Computer Organization
MCA 107 25
 Register A Register B Register C Register D
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

B1 C 1 D1 B2 C2 D2 B3 C 3 D 3 B4 C 4 D 4

0 0 0 0
4 x1 4 x1 4 x1 4 x1
MUX MUX MUX MUX

x
select
y

4-line bus
Computer Organization MCA 107 26
 Transfer From Bus To A Destination Register
Bus lines

Load
Reg. R0 Reg. R1 Reg. R2 Reg. R3

D0 D1 D2 D3
z E (enable)
Select 2x4
w
Decoder

Three-State Bus Buffers

Normal input A Output Y=A if C=1
Control input C High-impedence if C=0

Bus line with three-state buffers

Bus line for bit 0
A0
B0
C0
D0

S0 0
Select S1
1
2
Enable 3
Computer Organization MCA 107 27
 Bus Transfer In RTL
• Depending on whether the bus is to be mentioned
explicitly or not, register transfer can be indicated as
either
R2  R1

or BUS  R1, R2  BUS

• In the former case the bus is implicit, but in the latter, it is

explicitly indicated

Computer Organization MCA 107 28

 Memory (RAM)
• Memory (RAM) can be thought as a sequential circuits
containing some number of registers
• These registers hold the words of memory
• Each of the r registers is indicated by an address range from 0
to r-1and each register (word) can hold n bits of data
• Assume the RAM contains r = 2k words. It needs the following
– n data input lines
– n data output lines data input lines
– k address lines n
address lines
– A Read control line k RAM
Read
– A Write control line unit
Write
n
data output lines
Computer Organization MCA 107 29
 Memory Transfer
• Collectively, the memory is viewed at the register level as a
device, M.
• We must specify which address in memory we will be using
and it is done by indexing memory references
• Memory is usually accessed in computer systems by putting the
desired address in a special register, the Memory Address
Register (MAR, or AR)
• When memory is accessed, the contents of the MAR get sent to
the memory unit’s address lines M

Memory Read
AR
unit Write

Data out Data in

Computer Organization MCA 107 30

 Memory Read
• To read a value from a location in memory and load it
into a register, the register transfer language notation
looks like this:R1←M[MAR]
• This causes the following to occur
– The contents of the MAR get sent to the memory
address lines
– A Read (= 1) gets sent to the memory unit
– The contents of the specified address are put on the
memory’s output data lines
– These get sent over the bus to be loaded into register
R1

Computer Organization MCA 107 31

 Memory Write
• To write a value from a register to a location in
memory looks like this in register transfer
language: R1←M[MAR]

• This causes the following to occur

– The contents of the MAR get sent to the
memory address lines
– A Write (= 1) gets sent to the memory unit
– The values in register R1 get sent over the bus
to the data input lines of the memory
– The values get loaded into the specified
address in the memory

Computer Organization MCA 107 32

 Lecture - 4

Arithmetic Micro-operations

Computer Architecture BCA 203 33

 Bus Transfer

• Common Bus: It is a structure that consists of

a set of common lines , one for each bit of a
register, through which binary information is
transferred one at a time.
For e.g. If we have four registers and size of
each register is of 4-bit.

Computer Architecture BCA 203 34

 How to design a common bus? (in
general)
Problem : Design a n-line common bus system
that will multiplex ‘k’ registers of ‘n’ – bits
each.
Solution :
• No. of multiplexers required = n
• Size of multiplexers=k X 1
• No. of data lines = k
• No. of select lines = m such that 2m = k
Computer Architecture BCA 203 35
 Memory Transfer

• Read: Transfer of information from a memory

word to the outside environment.
• Write : Transfer of new information to be
stored into the memory.

Read: DR ← M[AR]
Write: M[AR] ← R1

Computer Architecture BCA 203 36

 Microoperations

• Computer system microoperations are of four types:

- Register transfer microoperations

- Arithmetic microoperations
- Logic microoperations
- Shift microoperations

Computer Architecture BCA 203 37

 Arithmetic Micro operations
• The basic arithmetic micro operations are
– Addition
– Subtraction
– Increment
– Decrement

• The additional arithmetic micro operations are

– Add with carry
– Subtract with borrow
– Transfer/Load
– etc. …

Computer Architecture BCA 203 38

Summary of Typical Arithmetic Micro
operations
– R3  R1 + R2 [Contents of R1 plus R2 transferred to R3]
– R3  R1 - R2 [Contents of R1 minus R2 transferred to R3]
– R2  R2’ [Complement the contents of R2 ]
– R2  R2’+ 1 [2's complement the contents of R2
(negate)]
– R3  R1 + R2’+ 1 [Subtraction]
– R1  R1 + 1 [Increment]
– R1  R1 - 1 [Decrement]

Computer Architecture BCA 203 39

 Binary Adder

B3 A3 B2 A2 B1 A1 B0 A0

FA C3 FA C2 FA C1 FA C0

C4 S3 S2 S1 S0

Computer Architecture BCA 203 40

 Binary Adder-Subtractor

B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1 C0
FA FA FA FA

C4 S3 S2 S1 S0
Computer Architecture BCA 203 41
 Binary Incrementer
A3 A2 A1 A0 1

x y x y x y x y
HA HA HA HA
C S C S C S C S

C4 S3 S2 S1 S0

Computer Architecture BCA 203 42

 Arithmetic Circuit Function Table
S1 S0 Cin Y OutputMicro operation
0 0 0 B D=A+B Add
0 0 1 B D = A + B + 1 Add with carry
0 1 0 B’ D = A + B’ Subtract with
borrow
0 1 1 B’ D = A + B’+ 1 Subtract
1 0 0 0 D=A Transfer A

1 0 1 0 D=A+1 Increment A
1 1 0 1 D=A-1 Decrement A
1 1 1 1 D=A Transfer A

Computer Architecture BCA 203 43

Computer Architecture BCA 203 44
 Lecture - 5

Logic Micro-operations and their

Applications
 Logic Microoperations
• Specify binary operations on the strings of bits in
registers
– Logic micro operations are bit-wise operations, i.e., they
work on the individual bits of data
– useful for bit manipulations on binary data
– useful for making logical decisions based on the bit value

A B F0 F1 F2 … F13 F14 F15

0 0 0 0 0 … 1 1 1
0 1 0 0 0 … 1 1 1
1 0 0 0 1 … 0 1 1
1 1 0 1 0 … 1 0 1

Computer Architecture BCA 203 46

 List Of Logic Microoperations
• Truth tables for 16 functions of 2 variables and the
corresponding 16 logic micro-operations

Boolean Micro-
Name
Function Operations
0000 F0 = 0 F0 Clear
0001 F1 = xy FAB AND
0010 F2 = xy' F  A  B’
0011 F3 = x FA Transfer A
0100 F4 = x'y F  A’ B
0101 F5 = y FB Transfer B
0110 F6 = x  y FAB Exclusive-OR
0111 F7 = x + y FAB OR
1000 F8 = (x + y)' F  A  B)’ NOR
1001 F9 = (x  y)' F  (A  B)’ Exclusive-NOR
1010 F10 = y' F  B’ Complement B
1011 F11 = x + y' FAB
1100 F12 = x' F  A’ Complement A
1101 F13 = x' + y F  A’ B
1110 F14 = (xy)' F  (A  B)’ NAND
1111 F15 = 1 F  all 1's Set to all 1's
Computer Architecture BCA 203 47
Hardware Implementation Of Logic Micro
operations
Ai
0
Bi

1
4X1 Fi
MUX
2

3 Select

S1
S0

Function table
S1 S0 Output -operation
0 0 F=AB AND
0 1 F = AB OR
1 0 F=AB XOR
1 1 F = A’ Complement

Computer Architecture BCA 203 48

 Applications Of Logic Micro operations
• Logic micro operations can be used to manipulate
individual bits or a portions of a word in a register
• Consider the data in a register A. In another register, B,
is bit data that will be used to modify the contents of A
– Selective-set A A+B
– Selective-complement A  A  B
– Selective-clear A  A • B’
– Mask (Delete) A A• B
– Clear A A B
– Insert  (A • B) + C
– Compare A A B
Computer Architecture BCA 203 49
 Selective Set
• In a selective set operation, the bit pattern in B is used to set
certain bits in A

1 1 0 0 At
1010B
1 1 1 0 At+1 (A  A + B)

• If a bit in B is set to 1, that same position in A gets set to 1,

otherwise that bit in A keeps its previous value

Computer Architecture BCA 203 50

 Selective Complement
• In a selective complement operation, the bit pattern in B is
used to complement certain bits in A

1 1 0 0 At
1010B
0 1 1 0 At+1 (A  A  B)

• If a bit in B is set to 1, that same position in A gets

complemented from its original value, otherwise it is
unchanged

Computer Architecture BCA 203 51

 Selective Clear

• In a selective clear operation, the bit pattern in B is used to

clear certain bits in A

1 1 0 0 At
1010B
0 1 0 0 At+1 (A  A  B’)

• If a bit in B is set to 1, that same position in A gets set to 0,

otherwise it is unchanged

Computer Architecture BCA 203 52

 Mask Operation

• In a mask operation, the bit pattern in B is used to clear

certain bits in A

1 1 0 0 At
1010B
1 0 0 0 At+1 (A  A  B)

• If a bit in B is set to 0, that same position in A gets set to 0,

otherwise it is unchanged

Computer Architecture BCA 203 53

 Clear Operation

• In a clear operation, if the bits in the same position in A and

B are the same, they are cleared in A, otherwise they are set
in A

1 1 0 0 At
1010B
0 1 1 0 At+1 (A  A  B)

Computer Architecture BCA 203 54

 Insert Operation
• An insert operation is used to introduce a specific bit pattern
into A register, leaving the other bit positions unchanged
• This is done as
– A mask operation to clear the desired bit positions, followed
by an OR operation to introduce the new bits into the
desired positions
– Example: Suppose you wanted to introduce 1010 into the
low order four bits of A:1101 1000 1011 0001A (Original)
1101 1000 1011 1010A (Desired)
Solution: Mask original A with 1111 1111 1111 0000, then
add 0000 0000 0000 1010 to intermediate result and
we get the desired result.

Computer Architecture BCA 203 55

 Lecture - 5

Logic Micro-operations and their

Applications
 Logic Microoperations
• Specify binary operations on the strings of bits in
registers
– Logic micro operations are bit-wise operations, i.e., they
work on the individual bits of data
– useful for bit manipulations on binary data
– useful for making logical decisions based on the bit value

A B F0 F1 F2 … F13 F14 F15

0 0 0 0 0 … 1 1 1
0 1 0 0 0 … 1 1 1
1 0 0 0 1 … 0 1 1
1 1 0 1 0 … 1 0 1

Computer Architecture BCA 203 57

 List Of Logic Microoperations
• Truth tables for 16 functions of 2 variables and the
corresponding 16 logic micro-operations

Boolean Micro-
Name
Function Operations
0000 F0 = 0 F0 Clear
0001 F1 = xy FAB AND
0010 F2 = xy' F  A  B’
0011 F3 = x FA Transfer A
0100 F4 = x'y F  A’ B
0101 F5 = y FB Transfer B
0110 F6 = x  y FAB Exclusive-OR
0111 F7 = x + y FAB OR
1000 F8 = (x + y)' F  A  B)’ NOR
1001 F9 = (x  y)' F  (A  B)’ Exclusive-NOR
1010 F10 = y' F  B’ Complement B
1011 F11 = x + y' FAB
1100 F12 = x' F  A’ Complement A
1101 F13 = x' + y F  A’ B
1110 F14 = (xy)' F  (A  B)’ NAND
1111 F15 = 1 F  all 1's Set to all 1's
Computer Architecture BCA 203 58
Hardware Implementation Of Logic Micro
operations
Ai
0
Bi

1
4X1 Fi
MUX
2

3 Select

S1
S0

Function table
S1 S0 Output -operation
0 0 F=AB AND
0 1 F = AB OR
1 0 F=AB XOR
1 1 F = A’ Complement

Computer Architecture BCA 203 59

 Applications Of Logic Micro operations
• Logic micro operations can be used to manipulate
individual bits or a portions of a word in a register
• Consider the data in a register A. In another register, B,
is bit data that will be used to modify the contents of A
– Selective-set A A+B
– Selective-complement A  A  B
– Selective-clear A  A • B’
– Mask (Delete) A A• B
– Clear A A B
– Insert  (A • B) + C
– Compare A A B
Computer Architecture BCA 203 60
 Selective Set
• In a selective set operation, the bit pattern in B is used to set
certain bits in A

1 1 0 0 At
1010B
1 1 1 0 At+1 (A  A + B)

• If a bit in B is set to 1, that same position in A gets set to 1,

otherwise that bit in A keeps its previous value

Computer Architecture BCA 203 61

 Selective Complement
• In a selective complement operation, the bit pattern in B is
used to complement certain bits in A

1 1 0 0 At
1010B
0 1 1 0 At+1 (A  A  B)

• If a bit in B is set to 1, that same position in A gets

complemented from its original value, otherwise it is
unchanged

Computer Architecture BCA 203 62

 Selective Clear

• In a selective clear operation, the bit pattern in B is used to

clear certain bits in A

1 1 0 0 At
1010B
0 1 0 0 At+1 (A  A  B’)

• If a bit in B is set to 1, that same position in A gets set to 0,

otherwise it is unchanged

Computer Architecture BCA 203 63

 Mask Operation

• In a mask operation, the bit pattern in B is used to clear

certain bits in A

1 1 0 0 At
1010B
1 0 0 0 At+1 (A  A  B)

• If a bit in B is set to 0, that same position in A gets set to 0,

otherwise it is unchanged

Computer Architecture BCA 203 64

 Clear Operation

• In a clear operation, if the bits in the same position in A and

B are the same, they are cleared in A, otherwise they are set
in A

1 1 0 0 At
1010B
0 1 1 0 At+1 (A  A  B)

Computer Architecture BCA 203 65

 Insert Operation
• An insert operation is used to introduce a specific bit pattern
into A register, leaving the other bit positions unchanged
• This is done as
– A mask operation to clear the desired bit positions, followed
by an OR operation to introduce the new bits into the
desired positions
– Example: Suppose you wanted to introduce 1010 into the
low order four bits of A:1101 1000 1011 0001A (Original)
1101 1000 1011 1010A (Desired)
Solution: Mask original A with 1111 1111 1111 0000, then
add 0000 0000 0000 1010 to intermediate result and
we get the desired result.

Computer Architecture BCA 203 66

 Lecture -7

Basic Computer Organization

 Introduction
• Every different processor type has its own design (different
registers, buses, micro operations, machine instructions, etc)
• It contains
– Many registers
– Multiple arithmetic units, for both integer and floating
point calculations
– The ability to pipeline several consecutive instructions to
speed execution
• We will use basic computer model to introduce processor
organization and the relationship of the RTL model to the
higher level computer processor

Computer Architecture BCA 203 68

 The Basic Computer
• The Basic Computer has two components, a processor and
memory
• The memory has 4096 words in it
– 4096 = 212, so it takes 12 bits to select a word in memory
• Each word is 16 bits long
CPU RAM
0

15 0

4095

Computer Architecture BCA 203 69

 Instructions
• Program
– A sequence of (machine) instructions
• (Machine) Instruction
– A group of bits that tell the computer to perform a
specific operation (a sequence of micro-operation)
• The instructions of a program, along with any needed data
are stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the
instruction into the sequence of micro operations
necessary to implement it

Computer Architecture BCA 203 70

 Instruction Format
• A computer instruction is often divided into two parts
– An opcode (Operation Code) that specifies the operation for
that instruction
– An address that specifies the registers and/or locations in
memory to use for that operation
• In the Basic Computer, since the memory contains 4096 (= 212)
words, we needs 12 bit to specify which memory address this
instruction will use
• In the Basic Computer, bit 15 of the instruction specifies the
addressing mode (0: direct addressing, 1: indirect addressing)
• Since the memory words, and hence the instructions, are 16 bits
long, that leaves 3 bits for the instruction’s opcode

Computer Architecture BCA 203 71

 Addressing Modes
• The address field of an instruction can represent
in two broad ways.
– Direct address: the address in memory of the
data to use (the address of the operand).

– Indirect address: the address in memory of the

address in memory of the data to use.

• There are many more addressing modes as well.

Computer Architecture BCA 203 72

 Addressing Modes (contd…)
Direct addressing Indirect addressing

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand

1350 Operand

+ +

AC AC

Computer Architecture BCA

73
203
 Lecture-8

Basic Computer Registers

 Basic Computer Registers
Registers in the Basic Computer
11 0
PC
Memory
11 0
4096 x 16
AR

15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

Computer Architecture BCA 203 75

 Basic Computer Registers (contd…)
– DR 16 Data Register Holds memory
operand
– AR 12 Address Register Holds address for memory
– AC 16 Accumulator Processor register
– IR 16 Instruction Register Holds instruction code
– PC 12 Program Counter Holds address of instruction
– TR 16 Temporary Register Holds temporary data
– INPR 8 Input Register Holds input character
– OUTR 8 Output Register Holds output character

Computer Architecture BCA 203 76

 Processor Registers
• A processor has many registers to hold instructions,
addresses, data, etc
• The processor has a register, the Program Counter (PC) that
holds the memory address of the next instruction to get
– Since the memory in the Basic Computer only has 4096
locations, the PC only needs 12 bits
• The Address Register (AR) is a 12 bit register in the Basic
Computer to hold the memory address
• When an operand is found, using either direct or indirect
addressing, it is placed in the Data Register (DR). The
processor then uses this value as data for its operation
• The Basic Computer has a single general purpose register –
the Accumulator (AC)

Computer Architecture BCA 203 77

• The significance of a general purpose register is that it can be
referred to in instructions
– e.g. load AC with the contents of a specific memory
location; store the contents of AC into a specified memory
location
• Often a processor will need a scratch register to store
intermediate results or other temporary data; in the Basic
Computer this is the Temporary Register (TR)
• The Input Register (INPR) holds an 8 bit character received
from an input device
• The Output Register (OUTR) holds an 8 bit character to be send
to an output device

Computer Architecture BCA 203 78

 Common Bus System

• The registers in the Basic Computer are

connected using a bus

• This gives a savings in circuitry over

complete connections between registers

Computer Architecture BCA 203 79

 Common Bus System
S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2

LD INR CLR

DR 3

LD INR CLR
E
ALU AC 4

LD INR CLR

INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus
Computer Architecture BCA 203 80
 Common Bus System
Read
INPR
Memory Write
4096 x 16
Address E ALU

AC

L I C

L I C L

L I C DR IR L I C

PC TR

AR OUTR LD

L I C

7 1 2 3 4 5 6

16-bit Common Bus

S0 S1 S2
Computer Architecture BCA 203 81
 Common Bus System
• Three control lines, S2, S1, and S0 control which register
the bus selects as its input

• Either one of the registers will have its load signal

activated, or the memory will have its read signal
activated
– Will determine where the data from the bus gets
loaded
• The 12-bit registers, AR and PC, have 0’s loaded onto the
bus in the high order 4 bit positions
• When the 8-bit register OUTR is loaded from the bus, the
data comes from the low order 8 bits on the bus

Computer Architecture BCA 203 82

 Lecture-9 & 10

Computer Instructions and Timing

and Control Unit
 Basic Computer Instructions
• Basic Computer Instruction Format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation

Computer Architecture BCA203 84

 Basic
Hex Code
Computer Instructions
Symbol I = 0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
85
Computer Architecture BCA203 85
 Instruction Set Completeness
A computer should have a set of instructions so that the user can
construct machine language programs to evaluate any function
that is known to be computable.
• Instruction Types
Functional Instructions
- Arithmetic, logic, and shift instructions
(ADD, CMA, INC, CIR, CIL, AND, CLA)
Transfer Instructions
- Data transfers between the main memory
and the processor registers (LDA, STA)
Control Instructions
- Program sequencing and control (BUN, BSA, ISZ)
Input/Output Instructions
- Input and output (INP, OUT)

Computer Architecture BCA203 86

 Timing And Control Unit
• Control unit (CU) of a processor translates from machine
instructions to the control signals for the micro operations
that implement them.
• Timing for all registers in the basic computer is controlled
by a master clock.
• Clock pulses donot change the state of a register unless the
register is enabled by the control signal generated by CU.

Computer Architecture BCA203 87

 Types Of Control Unit
• Control units are implemented in one of two ways:
1. Hardwired Control Unit
– CU is made up of sequential and combinational circuits to
generate the control signals.
– Advantage: Can be optimized to produce fast mode of
operation.
– Disadvantage: Requires changes in wiring, if the designed
has to be modified.
2. Micro programmed Control Unit
– A control memory on the processor contains micro
programs that activate the necessary control signals.
– Advantage: Any required changes can be done by updating
the micro program.

Computer Architecture BCA203 88

 Hardwired Timing And Control Unit
Control unit of Basic Computer
Instruction register (IR)
15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I Combinational
D7 Control Control
logic signals

T15
T0

15 14 . . . . 2 1 0
4 x 16
decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

Computer Architecture BCA203 89

 Timing Signals
- Generated by 4-bit sequence counter and 416 decoder
- The SC can be incremented or cleared.
- Example: T0, T1, T2, T3, T4, T0, T1, . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3
is active i.e., D3T4: SC 0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

Computer Architecture BCA203 90

 Lecture-11

Instruction Cycle and Register-

Reference Instructions
 Instruction Cycle
• In Basic Computer, a machine instruction is executed in the
following cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the
instruction has an indirect address
4. Execute the instruction
• After an instruction is executed, the cycle starts again at
step 1, for the next instruction
• Note: Every different processor has its own (different)
instruction cycle

Computer Architecture BCA 203 92

 Fetch And Decode
• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1
S2
T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus

Computer Architecture BCA 203 93

 Determine The Type Of InstructionStart
SC  0

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3:Nothing
D7I‘ T3: Execute a register-reference instr.
D 7I T 3 : Execute an input-output instr.
Computer Architecture BCA 203 94
 Register Reference Instructions
Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3
r = D7 IT3 => Register Reference Instruction
Bi = IR(i) , i=0,1,2,...,11
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S Architecture
Computer  0 (S isBCAa start-stop
203 flip-flop) 95
 Lecture - 12

Memory Reference Instructions

 Memory Reference Instructions
Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

• The effective address of the instruction is in AR and was

placed there during timing signal T2 when I = 0, or during
timing signal T3 when I = 1
• Memory cycle is assumed to be short enough to complete in a
CPU cycle
• The execution of MR instruction starts with T4

Computer Architecture BCA 203 97

 Memory Reference Instruction
• AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC

• ADD to AC
D1T4: DR  M[AR] Read
operand
D1T5: AC  AC + DR, E  Cout, SC  0
Add to AC and store carry in E

Computer Architecture BCA 203 98

 Memory Reference Instruction
• LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0

• STA: Store AC
D3T4: M[AR]  AC, SC  0

• BUN: Branch Unconditionally

D4T4: PC  AR, SC  0

Computer Architecture BCA 203 99

 Memory Reference Instruction

• BUN instruction is an unconditional Jump instruction

from one memory location to another memory
location.

• If we want to come back to the old memory location,

then it will not be possible.

• For that, there is another instruction i.e., BSA.

Computer Architecture BCA 203 100

 Memory Reference Instructions

BSA: Branch and Save Return Address

D5T4: M[AR]  PC, PC  AR + 1
D5T5: PC  AR, SC  0
Memory, PC, AR at time T4 Memory, PC after execution
20 0 BSA 135 20 0 BSA 135
PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory
Computer Architecture BCA 203 Memory
101
 Memory Reference Instructions

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR,
if (DR = 0) then (PC  PC + 1), SC  0

Computer Architecture BCA 203 102

 FLOWCHART
Memory-reference instruction

AND ADD LDA STA

D0 T 4 D1 T 4 D2 T 4 D3T 4
DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC
SC  0

D0T 5 D1T 5 D2T 5

AC  AC  DR AC  AC + DR AC  DR
SC  0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4T 4 D5T 4 D6T 4

PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5T 5 D6T 5

PC  AR DR  DR + 1
SC  0
D6T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0
Computer Architecture BCA 203 103
 Lecture - 13

I/O Reference Instructions

• Input-Output Configuration

Input-output Serial Computer

terminal communication registers and
interface
flip-flops
Receiver
Printer interface OUTR FGO

AC

Transmitter
Keyboard interface INPR FGI

Serial Communications Path

Parallel Communications Path

INPR Input register - 8 bits

OUTR Output register - 8 bits
FGI Input flag - 1 bit
FGO Output flag - 1 bit
IEN Interrupt enable - 1 bit

Computer Architecture BCA 203 105

 Input-Output And Interrupt

• The terminal sends and receives serial information

• The serial info. from the keyboard is shifted into
INPR
• The serial info. for the printer is stored in the OUTR
• INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
• The flags are needed to synchronize the timing
difference between I/O device and the computer

Computer Architecture BCA 203 106

 Input-Output Instructions

D7IT3 = p
IR(i) = Bi, i = 6, …, 11
p: SC  0 Clear SC
INP pB11: AC(0-7)  INPR, FGI  0 Input char. to AC
OUT pB10: OUTR  AC(0-7), FGO  0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC  PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC  PC + 1) Skip on output flag
ION pB7: IEN  1 Interrupt enable on
IOF pB6: IEN  0 Interrupt enable off

Computer Architecture BCA 203 107

 I/O and Interrupt

Program-controlled Input/Output
• Program-controlled I/O
- Continuous CPU involvement
I/O takes valuable CPU time
- CPU slowed down to I/O speed
- Simple
- Least hardware
Input

LOOP, SKI DEV

BUN LOOP
INP DEV

Output
LOOP, LDA DATA
LOP, SKO DEV
BUN LOP
OUT DEV

Computer Architecture BCA 203 108

 Interrupt Initiated Input/Output
• Open communication only when some data has to be passed -->
interrupt.
• The I/O interface, instead of the CPU, monitors the I/O device.
• When the interface founds that the I/O device is ready for data
transfer, it generates an interrupt request to the CPU
• Upon detecting an interrupt, the CPU stops momentarily the task it
is doing, branches to the service routine to process the data transfer,
and then returns to the task it was performing.

•IEN (Interrupt-enable flip-flop):

- can be set and cleared by instructions.
- when cleared, the computer cannot be interrupted

Computer Architecture BCA 203 109

 Flowchart Of Interrupt Cycle

- The interrupt cycle is a HW implementation of a

branch and save return address operation.
- At the beginning of the next instruction cycle, the
instruction that is read from memory is in address 1.
- At memory address 1, the programmer must store a
branch instruction
that sends the control to an interrupt service routine
- The instruction that returns the control to the original
program is "indirect BUN 0"

Computer Architecture BCA 203 110

Computer Architecture BCA 203 111
 Lecture - 14

Design of Basic Computer

 Design of Basic Computer
• Hardware Components of BC
A memory unit: 4096 x 16.
Registers:
AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
Flip-Flops(Status): I, S, E, R, IEN, FGI, and FGO
Decoders: A 3x8 Opcode decoder and A 4x16
timing decoder
Common bus: 16 bits
Control logic gates:
Adder and Logic circuit: Connected to AC
Computer Architecture BCA 203 113
 contd…
• Control Logic Gates
 Input Controls of the nine registers
 Read and Write Controls of memory
Set, Clear, or Complement Controls of the
flip-flops
 S2, S1, S0 Controls to select a register for the
bus
AC, and Adder and Logic circuit
Computer Architecture BCA 203 114
Control Of Registers And Memory
• Scan all of the register transfer statements
that change the content of AR:
R’T0: AR  PC LD(AR)
R’T2: AR  IR(0-11) LD(AR)
D’7IT3: AR  M[AR] LD(AR)
RT0: AR  0 CLR(AR)
D5T4: AR  AR + 1 INR(AR)

Computer Architecture BCA 203 115

 contd…
12 12
From bus AR To bus
D'7
I
LD Clock
T3
T2 INR
CLR
R
T0
D
T4

Computer Architecture BCA 203 116

 Control of Flags
• pB7: IEN  1 (I/O Instruction)
• pB6: IEN  0 (I/O Instruction)
• RT2: IEN  0 (Interrupt)
• p = D7IT3 (Input/Output Instruction)
D7
I p
B7 J Q IEN
T3

B6
K
R
T2
Computer Architecture BCA 203 117
 Zero Address Instructions
• Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location
PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

 One Address Instructions
• Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location
LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC
 Two Address Instructions

• Expression: X = (A+B)*(C+D)
R1, R2 are registers MOV R1, A R1 = M[A]

M[] is any memory location ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = M[C]

ADD R2, D R2 = R2 + M[D]

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1
 Three Address Instructions
• Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location
ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2

 Advantages of Zero-Address, One-Address, Two-Address and
Three-Address Instructions

• Zero-address instructions
• They are simple and can be executed quickly since they do not require any
operand fetching or addressing. They also take up less memory space.
• One-address instructions
• They allow for a wide range of addressing modes, making them more flexible
than zero-address instructions. They also require less memory space than two or
three-address instructions.
• Two-address instructions
• They allow for more complex operations and can be more efficient than one-
address instructions since they allow for two operands to be processed in a
single instruction. They also allow for a wide range of addressing modes.
• Three-address instructions
• They allow for even more complex operations and can be more efficient than
two-address instructions since they allow for three operands to be processed in
 Disadvantages of Zero-Address, One-Address, Two-Address and
Three-Address Instructions

• Zero-address instructions
• They can be limited in their functionality and do not allow for much flexibility
in terms of addressing modes or operand types.
• One-address instructions
• They can be slower to execute since they require operand fetching and
addressing.
• Two-address instructions
• They require more memory space than one-address instructions and can be
slower to execute since they require operand fetching and addressing.
• Three-address instructions
• They require even more memory space than two-address instructions and can
be slower to execute since they require operand fetching and addressing.