UNIT - I Digital Computers: Introduction, Block diagram of Digital Computer, Definition of

Computer Organization, Computer Design and Computer Architecture. Register Transfer

Language and Micro operations: Register Transfer language, Register Transfer, Bus and
memory transfers, Arithmetic Micro operations, logic micro operations, shift micro operations,
Arithmetic logic shift unit. Basic Computer Organization and Design: Instruction codes,
Computer Registers Computer instructions, Timing and Control, Instruction cycle, Memory
Reference Instructions, Input – Output and Interrupt.

Digital computers

A computer system is subdivided into two functional entities: Hardware and Software. The hardware
consists of all the electronic components and electromechanical devices that comprise the physical
entity of the device. The software of the computer consists of the instructions and data that the
computer manipulates to perform various data-processing tasks.
The Central Processing Unit (CPU)
contains an arithmetic and logic unit
for manipulating data, a number of
registers for storing data, and a
control circuit for fetching and
executing instructions.
The memory of a computer contains
storage for instructions and data. Its is
called a random access
memory(RAM) because the CPU can
access any location in memory at
random and retrieve the binary
information within a fixed interval of time
The input and output processor(IOP) contains electronic circuits for communicating and controlling
the transfer of information between the computer and the outside world.
The input and output devices connected to the computer include keyboards, printers, terminals, disk
drives an other communication devices.
Computer organization is concerned with the way the hardware components operate and the way they
are connected together to form the computer system. The various components are assumed to be in
place and task is to investigate the organizational structure to verify that the computer parts operate as
intended.
Computer design is concerned with the hardware design of the computer. Once the computer
specification are formulated, it is the task of the designer to develop hardware for the system. Computer
design is concerned with the determination of what hardware should be used and how the parts should
be connected.
Computer architecture is concerned with the structure and behaviour of the computer as seen by the
user. It includes the information formats, instruction set, and techniques for addressing memory. The
architectural design of a computer system is concerned with the specification of the various functional
modules, such as processor and memories, and structuring them together into a computer system.
Register Transfer Language
The Register Transfer Language is the symbolic representation of notations used to specify
the sequence of micro-operations.
In a computer system, data transfer takes place between processor registers and memory and
between processor registers and input-output systems. These data transfer can be represented
by standard notations given below:

o Notations R0, R1, R2..., and so on represent processor registers.

o The addresses of memory locations are represented by names such as LOC, PLACE,
MEM, etc.
o Input-output registers are represented by names such as DATA IN, DATA OUT and so
on.
o The content of register or memory location is denoted by placing square brackets
around the name of the register or memory location.

Register Transfer

The term Register Transfer refers to the availability of hardware logic circuits that can perform
a given micro-operation and transfer the result of the operation to the same or another register.
Most of the standard notations used for specifying operations on various registers are stated
below.

• The register that holds an address for the memory unit is usually called a memory
address register is designated by MAR.
• Program Counter PC is a 16bit register which holds the next instruction's address.
The symbol PC( 0-7)or PC(L)
refers to the low order byte and
PC(8-15) or PC(H) to the high
order byte.
• Instruction Register IR holds the
instruction being executed.
• R1 (Processor Register).
• We can also indicate individual
bits by placing them in
parenthesis. For instance, PC (8-
15), R2 (5), etc.
• Data Transfer from one register to another register is represented in symbolic form
by means of replacement operator. For instance, the following statement denotes a
transfer of the data of register R1 into register R2.
R2 ← R1
Transfer to occur only a under a predetermined control condition. This can be shown by
following if-then statement:

If (P=1) then (R2 ← R1); Here P is a control signal generated in the control section.
the data transfer operation under a specific control function (P) is given by

P: R2 ← R1

Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs of the register
R1 are connected to the 'n' inputs of register R2. A load input is activated by the control variable
'P' which is transferred to the register R2. It is assumed that the control variable is synchronized
with the same clock as the one applied to the register.

The statement T: R2←R1,R1←R2 denotes an operation that exchanges the contents of two
registers during one common clock pulse provided that T=1

Bus and Memory Transfers

A digital system composed of many registers, and paths must be provided to transfer
information from one register to another. The number of wires connecting all of the registers
will be excessive if separate lines are used between each register and all other registers in the
system.
A bus structure, on the other hand, is more efficient for transferring information between
registers in a multi-register configuration system.
A bus consists of a set of common lines, one for each bit of register, through which binary
information is transferred one at a time. Control signals determine which register is selected by
the bus during a particular register transfer.
The following block diagram shows a Bus system for four registers. It is constructed with the
help of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two selection
inputs (S1 and S2).
We have used labels to make it more convenient for you to understand the input-output
configuration of a Bus system for four registers. For instance, output 1 of register A is
connected to input 0 of MUX1.
The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers.
The selection lines choose the four bits of one register and transfer them into the four-line
common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four
multiplexers are selected and applied to the outputs that forms the bus. This, in turn, causes the
bus lines to receive the content of register A since the outputs of this register are connected to
the 0 data inputs of the multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content
provided by register B.

A bus system can also be constructed using three-state gates instead of multiplexers.

The three state gates can be considered

as a digital circuit that has three gates, two
of which are signals equivalent to logic 1
and 0 as in a conventional gate. However,
the third gate exhibits a high-impedance
state.

The most commonly used three state gates in case of the bus system is a buffer gate.
The following diagram demonstrates the construction of a bus system with three-state buffers.
The outputs generated by the four
buffers are connected to form a single
bus line.

o Only one buffer can be in active

state at a given point of time.
o The control inputs to the buffers
determine which of the four normal
inputs will communicate with the bus
line.
o A 2 * 4 decoder ensures that no
more than one control input is active at
any given point of time.

Memory Transfer
Most of the standard notations used for specifying operations on memory transfer are stated
below.
o The transfer of information from a memory unit to the user end is called
a Read operation.
o The transfer of new information to be stored in the memory is called a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the memory transfer
operations.
o The address register is designated by AR and the data register by DR.
o Thus, a read operation can be stated as:
Read: DR ← M [AR]
o The Read statement causes a transfer
of information into the data register
(DR) from the memory word (M)
selected by the address register (AR).
o And the corresponding write operation
can be stated as: Write: M [AR] ← R1

The Write statement causes a transfer of information from register R1 into the memory word
(M) selected by address register (AR).
A micro-operation is a simple operation performed on the data stored in one or more registers. They
transfer the data between registers. There are four types of micro-operations.

• Register micro-operations
• Arithmetic micro-operations
• Logic micro-operations
• Shift micro-operations

Arithmetic Micro-operations
In general, the Arithmetic Micro-operations deals with the operations performed on numeric
data stored in the registers.
The basic Arithmetic Micro-operations are classified in the following categories:
1. Addition
2. Subtraction
3. Increment
4. Decrement

Some additional Arithmetic Micro-operations are classified as:

1. Add with carry
2. Subtract with borrow
The following table shows the symbolic representation of various Arithmetic Micro-
operations.

Add Micro-Operation: R3 ← R1 + R2 The above statement instructs the data or contents of

register R1 to be added to data or content of register R2 and the sum should be transferred to
register R3.
Subtract Micro-Operation: Let us again take an example: R3 ← R1 + R2' + 1 In subtract
micro-operation, instead of using minus operator we take 1's compliment and add 1 to the
register which gets subtracted, i.e R1 - R2 is equivalent to R3 ← R1 + R2' + 1
Increment/Decrement Micro-Operation: Increment and decrement micro-operations are
generally performed by adding and subtracting 1 to and from the register respectively. R1 ←
R1 + 1, R1 ← R1–1
Binary Adder
• The Add micro-operation requires registers that can hold the data and the digital
components that can perform the arithmetic addition.
 • A Binary Adder is a digital circuit that performs the arithmetic sum of two binary
numbers provided with any length.
• A Binary Adder is constructed using full-adder circuits connected in series, with the
output carry from one full-adder connected to the input carry of the next full-adder.

The following block diagram shows the interconnections of four full-adder circuits to provide
a 4-bit binary adder.

o The augend bits (A) and the addend bits (B) are designated by subscript numbers from
right to left, with subscript '0' denoting the low-order bit.
o The carry inputs starts from C0 to C3 connected in a chain through the full-adders. C4
is the resultant output carry generated by the last full-adder circuit.
o The output carry from each full-adder is connected to the input carry of the next-high-
order full-adder.
o The sum outputs (S0 to S3) generates the required arithmetic sum of augend and addend
bits.
o The n data bits for the A and B inputs come from different source registers. For
instance, data bits for A input comes from source register R1 and data bits for B input
comes from source register R2.
o The arithmetic sum of the data inputs of A and B can be transferred to a third register
or to one of the source registers (R1 or R2).

Binary Adder-Subtractor
Note: The 2's compliment can be obtained by taking the 1's compliment and adding one to the least significant
pair of bits. The 1's compliment can be implemented with inverters, and one can be added to the sum through
the input carry.

The Arithmetic micro-operations like addition and subtraction can be combined into one
common circuit by including an exclusive-OR gate with each full adder.
The block diagram for a 4-bit adder-subtractor circuit can be represented as:

o When the mode input (M) is at a low logic, i.e. '0', the circuit act as an adder and when
the mode input is at a high logic, i.e. '1', the circuit act as a subtractor.
o The exclusive-OR gate connected in series receives input M and one of the inputs B.
o When M is at a low logic, we have B⊕ 0 = B.
The full-adders receive the value of B, the input carry is 0, and the circuit performs A
plus B.
o When M is at a high logic, we have B⊕ 1 = B' and C0 = 1.
The B inputs are complemented, and a 1 is added through the input carry. The circuit
performs the operation A plus the 2's complement of B.

Binary Incrementor
The increment micro-operation adds one binary value to the value of binary variables stored in
a register. For instance, a 4-bit register has a binary value 0110, when incremented by one the
value becomes 0111. The increment micro-operation is best implemented by a 4-bit
combinational circuit incrementer. A 4-bit combinational circuit incrementer can be
represented by the following block diagram.

o A logic-1 is applied to one of the inputs of least significant half-adder, and the other
input is connected to the least significant bit of the number to be incremented.
o The output carry from one half-adder is connected to one of the inputs of the next-
higher-order half-adder.
o The binary incrementer circuit receives the four bits from A0 through A3, adds one to
it, and generates the incremented output in S0 through S3.
o The output carry C4 will be 1 only after incrementing binary 1111.
Logic Micro operation
Logic micro-operations are used on the bits of data stored in registers. These micro-operations
treat each bit independently and create binary variables from them.
There are a total of 16 micro-operations available. These are-

The below diagram shows the truth table for all the 16 logic micro-operations mentioned
above. Here, x and y are the variables or registers in which the data is stored and F0, F1,
….., F15 are the outputs that occur after performing these logic micro-operations.

Let us consider the X-OR micro-operation with the contents of two registers R1 and R2.
P: R1 ← R1 X-OR R2 or P: R1←R1⊕R2
1010 Content of R1
1100 Content of R2
0110 Content of R1 after P = 1
Shift Micro operations
Shift micro-operations are those micro-operations that are used for serial transfer of
information. These are also used in conjunction with arithmetic micro-operation, logic micro-
operation, and other data-processing operations.

Symbolic Designation Description

R ←R1 shl R Shift-left register R

R ←R1 shr R Shift-right register R

R ←R1 cil R Circular shift-left register R

R ←R1 cir R Circular shift-right register R

R ←R1 ashl R Arithmetic shift-left R

R ←R1 ashr R Arithmetic shift-right R

There are three types of shifts micro-operations:
1. Logical :
It transfers the 0 zero through the serial input.
We use the symbols shl for logical shift-left and
shr for shift-right.

Logical Shift Left –

In this shift one position moves each bit to the left
one by one. The Empty least significant bit (LSB) is
filled with zero (i.e, the serial input), and the most
significant bit (MSB) is rejected .
Right Logical Shift –
In this one position moves each bit to the right one by one and the least significant bit(LSB)
is rejected and the empty MSB is filled with zero .
Circular:
The circular shift circulates the bits in the sequence of the register around the both ends
without any loss of information.
Arithmetic:
This micro-operation shifts a signed binary number to the left
or to the right position. In an arithmetic shift-left, it multiplies
a signed binary number by 2 and In an arithmetic shift-right,
it divides the number by 2.
Left Arithmetic Shift –
In this one position moves each bit to the left one by one.
The empty least significant bit (LSB) is filled with zero and
the most significant bit (MSB) is rejected. Same as the Left
Logical Shift.
Arithmetic Logic shift unit(ALSU)
A computer systems create use of several storage registers that are linked to a typical
operational unit is known as the arithmetic and logic unit (ALU). ALU is the central and one
of the most essential units internal the CPU of the computer.
All the logical and numerical operations of a computer are implemented here. The contents of
a particular register are arranged in the input of ALU. ALU implements the given operation
and then transfers it to the target register.
The one stage of an arithmetic logic shift unit is demonstrated in the figure. The subscript i
nominate a frequent stage. There are two inputs are used for both the arithmetic and logic
units.
A specific micro-operation is choosing with inputs S1 and S0 A 4 x 1 multiplexer at the output
select between an arithmetic output in and a logic output in. The data in the multiplexer are
chosen with inputs S3 and S2.
There are two data inputs to the multiplexer receive inputs Ai-1 for the shift-right operation and
Ai+1 for the shift-left operation. The circuit should be continued n times for an n-bit ALU.
The output carry
Ci+1 of a given
arithmetic stage
should be linked to the
input carry Ci of the
next stage in the
series. The input
carries to the first
stage is the input carry
Cin It can support a
selection variable for
the arithmetic
operations.
The circuit whose one
stage is given in the
below diagram
provides 8 arithmetic
operations, 4 logic
operations, and 2 shift operations, and Each operation is selected by the 5 variables S3, S2,
S1, S0, and Cin.

Instruction code
An instruction code is a group of bits that tells the computer to perform a specific operation
part.
Operation Code
The operation code of an instruction is a group of bits that define operations such as add,
subtract, multiply, shift and compliment. The number of bits required for the operation code
depends upon the total number of operations available on the computer. The operation code
must consist of at least n bits for a given 2^n operations. The operation part of an instruction
code specifies the operation to be performed.
Register Part
The operation must be performed on the data stored in registers. An instruction code therefore
specifies not only operations to be performed but also the registers where the operands(data)
will be found as well as the registers where the result has to be stored.

Stored program organization

The ability to store and execute
instructions is the most important
property of a general-purpose computer.
That type of stored program concept is
called stored program organization.
➢ The simplest way to organize a
computer is to have one processor
register and an instruction code format
with two parts.
the first part specifies the operation to be
performed and the second specifies an
address.
➢ Instruction are stored in one section of
memory and data in another.
➢ For a memory unit with 4096 words we need 12 bits to specify an address since 212 = 4096.

➢ If we store each instruction code in one 16-bit memory word, we have available four bits
for the operation code (abbreviated opcode) to specify one out of 16 possible operations, and
12 bits to specify the address of an operand
Accumulator (AC): Computers that have a single-processor register usually assign to it the
name accumulator and label it AC. The operation is performed with the memory operand and
the content of AC.
Addressing modes
The address field for instruction can be represented in two different ways are as follows −

• Direct Addressing − It uses the address of the operand.

• Indirect Addressing − It facilitates the address as a pointer to the operand.
The address of the operand or the target address is called the effective address.
Effective Address (EA) − It defines the address that can be executed as a target address for a branch
type instruction or the address that can be used directly to create an operand for a computation type
instruction, without creating any changes.

A direct address instruction is

shown in Fig a.

➢ It is placed in address 22 in
memory. The I bit is 0, so the
instruction is recognized as a direct
address instruction. The opcode
specifies an ADD instruction, and
the address part is the binary
equivalent of 300.

➢ The control finds the operand in

memory at address 300 and adds it
to the content of AC.

➢ The instruction in address 20

shown in fig b has a mode bit I = 1.

➢ Therefore, it is recognized as an
indirect address instruction.

➢ The address part is the binary

equivalent of 200. The control goes to address 200 to find the address of the operand. The
address of the operand in this case is 1200.

➢ The operand found in address 1200 is then added to the content of AC.
➢ The effective address to be the address of the operand in a computation-type instruction or
the target address in a branch-type instruction.

➢ Thus the effective address in the instruction of Fig. a is 300 and in the instruction of Fig b
is 1200.
Computer Registers
Registers are a type of computer memory used to quickly accept, store, and transfer
data and instructions that are being used immediately by the CPU. The registers used by the
CPU are often termed as Processor registers. A processor register may hold an instruction, a
storage address, or any data (such as bit sequence or individual characters).

The computer needs processor registers for manipulating data and a register for holding a
memory address. The register holding the memory location is used to calculate the address of
the next instruction after the execution of the current instruction is completed.

Following is the list of some of the most common registers used in a basic
computer:

Register symbol Number of bits Function

Data register DR 16 Holds memory operand
Address register AR 12 Holds address for the memory
Accumulator AC 16 Processor register
Instruction register IR 16 Holds instruction code
Program counter PC 12 Holds address of the instruction
Temporary register TR 16 Holds temporary data
Input register INPR 8 Carries input character
Output register OUTR 8 Carries output character
 o The Memory unit has a capacity of 4096 words, and each word contains 16 bits.
o The Data Register (DR) contains 16 bits which hold the operand read from the memory
location.
o The Memory Address Register (MAR) contains 12 bits which hold the address for the
memory location.
o The Program Counter (PC) also contains 12 bits which hold the address of the next
instruction to be read from memory after the current instruction is executed.
o The Accumulator (AC) register is a general purpose processing register.
o The instruction read from memory is placed in the Instruction register (IR).
o The Temporary Register (TR) is used for holding the temporary data during the
processing.
o The Input Registers (INPR) holds the input characters given by the user.
o The Output Registers (OUTR) holds the output after processing the input data.

Common bus system

Basic Components of Common Bus System

• Common Bus System uses a multiplexer to implement Common BUS.
• Memory and all Registers are connected through a common bus system.
• We consider 3 select lines (S0, S1, and S2) because we are using 7 inputs
 to multiplexer as shown in the following diagram. With the help of 3 select lines,
8 inputs to multiplexer can be given.
• Select lines are 2n. It means how many total inputs can be added.
As 23=8x1(called 8 inputs and one output).
• 6 registers (AR, PC, DR, AC, IR and TR) and memory unit are connected to common bus.
The DR (Data Register) is also connected with the ADDER and Logic Unit to perform
operations on data through data Bus.
• INPTR (Input register) is not connected with the common bus. it receives data directly for
Input device and sends it to Adder and Logic unit (part of ALU) for operations (+, -,*, /) and
then pass it to Accumulator register. The adder and logic unit also contains a carry bit called
(E) in case of addition.
OUTR (Output Register) does not send data to a common bus or any other register because it
sends directly to the output device but it receives data from the common bus.

There are multiple registers and their functions which are as follows −

• Load (LD) − During the next clock pulse transition the information from the bus is
transmitted to the register whose load (LD) input is enabled.
• Memory Unit − When the write input of the memory is activated, it holds the content
of the bus. When the read input is activated, the memory places the 16-bit output onto
the bus with the selection variables being S2S1 S0 = 111..
• Increment (INR) and Clear (CLR) − When the INR signal is enabled, the contents of
the specified register are incremented. The contents are cleared when the CLR signal is
enabled.
• Address Registers (AR) − The address of the memory for the next read and write
operation is determined. It receives or sends an address from or to the bus when
selection inputs S2S1 S0=001 is used and the load is enabled. With inputs INR and CLR,
the address gets incremented or cleared.
• Program Counter (PC) − The address of the next instruction that is to be read from
the memory is saved. It receives or sends an address from or to the bus when selection
inputs S2S1 S0 = 010is applied and the load input is enabled. With inputs INR and CLR,
the address gets incremented or cleared.
• Data Register (DR) − The data register includes the data to be written into memory or
data that is to be read from the memory. It receives or sends an address from or to the
bus when selection inputs are S2S1 S0 = 011 applied and the load input is enabled. With
inputs INR and CLR, the address gets incremented or cleared.
• Accumulator (AC) − Accumulators are beneficial in executing the register micro-
operations including complement, shift, etc. The results acquired are again sent to the
accumulator. An accumulator stores the intermediate arithmetic and logic results.
• Instruction Registers (IR) − The IR stores the copy of the instruction that the
processor has to implement. The instruction that is read from the memory is stored in
 the IR. It receives or sends instruction code from or to the bus when selection inputs
S2S1 S0 = 111 are applied and the load input is enabled.
• Temporary Register (TR) − The temporary storage for variables or results is
supported by the temporary register. It receives or sends the temporary data from or to
the bus when selection inputs S2S1 S0 = 011 are applied and the load input is enabled.
With inputs INR and CLR, the address gets incremented or cleared.
• Input Registers (INPR) − It includes 8 bits to hold the alphanumeric input
information. Input device shifts its serial data into the 8-bit register. The data is moved
to AC via the adder/logic circuit with load enabled.
• Output Registers (OUTPR) − The data is received from AC and moved to the output
device.

Computer Instruction
Computer instructions are a set of machine language instructions that a particular processor
understands and executes. A computer performs tasks on the basis of the instruction provided.
An instruction comprises of groups called fields. These fields include:
o The Operation code (Opcode) field which specifies the operation to be performed.
o The Address field which contains the location of the operand, i.e., register or memory
location.
o The Mode field which specifies how the operand will be located.
Memory Reference Instruction
A memory-reference instruction uses 12 bits to specify an address and one bit to determine the
addressing mode I. I is the same as 0 for direct address and to 1 for indirect address.

Register Reference Instruction

The register reference instructions are identified by the operation code 111 with a 0 in the
leftmost bit (bit 15) of the instruction. It determines an operation on or a test of the AC register.
An operand from memory is not required because the additional 12 bits are used to determine
the operation or test to be implemented.

Input-Output Instruction
An input-output instruction does not require a reference to memory and is identified by the
operation code 111 with a 1 in the leftmost bit of the instruction. The remaining 12 bits can
determine the type of input-output operation or test implemented.
The type of instruction is identified by the computer control from the four bits in positions 12
through 15 of the instruction. If the three opcode bits in positions 12 through 14 are not similar
to 111, the instruction is a memory-reference type and the bit in position 15 is taken as the
addressing mode I. If the 3-bit opcode is similar to 111, the control then examines the bit in
position 15. If this bit is 0, the instruction is a register-reference type. If the bit is 1, the
instruction is an input-output type.
Symbol Hexadecimal Code Description
AND 0xxx 8xxx And memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store AC content in memory
BUN 4xxx Cxxx Branch Unconditionally
BSA 5xxx Dxxx Branch and Save Return
Address
ISZ 6xxx Exxx Increment and skip if 0
CLA 7800 Clear AC
CLE 7400 Clear E(overflow bit)
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC > 0
SNA 7008 Skip next instruction if AC < 0
SZA 7004 Skip next instruction if AC = 0
SZE 7002 Skip next instruction if E = 0
HLT 7001 Halt computer
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt On
IOF F040 Interrupt Off
Instruction Set Completeness:
A computer should have a set of instructions so that the user can construct machine language
programs to evaluate any function.

➢ The set of instructions are said to be complete if the computer includes a sufficient number
of instructions in each of the following categories: o Arithmetic, logical, and shift instructions
o Data Instructions (for moving information to and from memory and processor registers) o
Program control or Brach o Input and output instructions

➢ There is one arithmetic instruction, ADD, and two related instructions, complement
AC(CMA)and increment AC(INC). With these three instructions we can add and subtract
binary numbers when negative numbers are in signed-2's complement representation.

➢ The circulate instructions, CIR and CIL; can be used for arithmetic shifts as well as any
other type of shifts desired.

➢ There are three logic operations: AND, complement AC (CMA), and clear AC(CLA). The
AND and complement provide a NAND operation.

➢ Moving information from memory to AC is accomplished with the load AC (LDA)

instruction. Storing information from AC into memory is done with the store AC (STA)
instruction.

➢ The branch instructions BUN, BSA, and ISZ, together with the four skip instructions,
provide capabilities for program control and checking of status conditions.

➢ The input (INP} and output (OUT) instructions cause information to be transferred between
the computer and external devices.

Timing and Control:

The timing for all registers in the basic computer is controlled by a master clock generator.
➢ The control signals are generated in the control unit and provide control inputs for the
multiplexers in the common bus, control inputs in processor registers, and microoperations for
the accumulator.

➢ There are two major types of control organization: Hardwired control and
Microprogrammed control
The differences between hardwired and microprogrammed control are
Hardwired control Microprogrammed control
The control logic is implemented with gates, The control information is stored in a
flip-flops, decoders, and other digital control memory. The control memory is
circuits. programmed to initiate the required
sequence of microoperations
The advantage that it can be optimized to Compared with the hardwired control
produce a fast mode of operation operation is slow.
Requires changes in the wiring among the Required changes or modifications can be
various components if the design has to be done by updating the microprogram in
modified or changed. control memory.
Shows the block diagram of control unit which uses hardwired approach. It consists of
decoders, a sequence counter(SC) and combinational logic circuitry.

Fig shows how the instruction in the instruction register(IR) is used to generate control signals.
The instruction register is divided into three fields: I field, operation code field and bits 0
through 11. The 3:8 decoder decodes the operation code bits and output of this decoder are
used as an input for combinational logic circuitry. The four bit sequence counter counts from
0000 through 1111,i.e. (0 through 15 in decimal). These four bits are decoded by 4:16 decoder
to generate timing signals from 0 through 15. The I bit from IR is also connected to the
combinational control circuitry. Therefore, combinational control circuitry takes the input from
3:18 decoder, 4:16 decoder, I bit and bits 0 through 11 to generate control signals.

Along with the clock input SC has two other inputs: clear and increment. Initially, sequence
counter is cleared by activating clear input. Once the SC is cleared, clear signal is negated and
SC is incremented with every positive clock transition to produce the sequence of timing
signals T0, T1, T2, T3 and so on. If SC is not cleared, the timing signal will continue with T4, T5
up to T15 and back to T0. However, if SC is cleared in between, a new sequence will start from
T0, T1 and so on.

From fig it is observed that the SC is cleared to 0 in T4 if decoder output D2 is active(logic 1).
This can be expressed symbolically as D3T4: SC←0
Instruction Cycle
A program residing in the memory unit of a computer consists of a sequence of instructions.
These instructions are executed by the processor by going through a cycle for each instruction.

In a basic computer, each instruction cycle consists of the following phases:

1. Fetch instruction from memory.

2. Decode the instruction.
3. Read the effective address from memory.
4. Execute the instruction.
After the following four procedures are done, the control switches back to the first step and
repeats the similar process for the next instruction. Therefore, the cycle continues until
a Halt condition is met. The figure shows the phases contained in the instruction cycle.

T0:AR←PC
T1: IR←M[AR], PC←PC+1

At T0, the address from PC is transferred from PC to AR. The instruction read from the memory
is then placed in the IR during T1. At the same time, PC is incremented by one.
The fig shows the implementation of the first two register transfer statements in the common
bus system.
In T0:
1. The contents of PC are
placed onto the common
bus by enabling its EN
input by setting
S2S1S0=010.
2. contents of the common
bus are transferred to AR
by enabling its LD input.
In T1:
1. read input of the memory is
enabled by setting S2S1S0=111.
This places the contents of
memory onto the bus
2. the contents of common bus are
transferred to IR by enabling the
its LD input.
3. PC is incremented by enabling
the INR input of PC.

Determine the Type

of Instruction:
➢ The timing signal
that is active after the
decoding is T3.
➢ During time T3, the
control unit determine
the type of instruction
that was read from the
memory.
➢ The flowchart of fig.
shows the initial
configurations for the
instruction cycle and
also how the control
determines the
instruction cycle type
after the decoding.
➢ Decoder output D7
is equal to 1 if the
operation code is equal
to binary 111.
➢ If D7=1, the
instruction must be a
register-reference or
input-output type.
➢ If D7 = 0, the operation code must be one of the other seven values 000 through 110,
specifying a memory-reference instruction.
➢ Control then inspects the value of the first bit of the instruction, which is now available in
flip-flop. ➢ If D7 = 0 and I = 1, indicates a memory-reference instruction with an indirect
address. So it is then necessary to read the effective address from memory.
➢ If D7 = 0 and I = 0, indicates a memory-reference instruction with a direct address.
➢ If D7 = 1 and I = 0, indicates a register-reference instruction.
➢ If D7 = 01and I = 1, indicates an input-output instruction.
➢ The three instruction types are subdivided into four separate paths.
➢ The selected operation is activated with the clock transition associated with timing signal
T3.

Memory Reference Instructions

A memory-reference instruction
uses 12 bits to specify an address
and one bit to determine the
addressing mode I. I is the same
as 0 for direct address and to 1
for indirect address.
1. The decoded output Di
for i = 0, 1, 2, 3, 4, 5, and
6 from the operation
decoder that belongs to
each instruction is included in the table.
2. The effective address of the instruction is in the address register AR and was placed
there during timing signal T2 when I= 0, or during timing signal T3 when I = 1.
3. The execution of the memory-reference instructions starts with timing signal T4.

AND to AC:
This is an instruction that performs the AND logic operation on pairs of bits in AC and the memory
word specified by the effective address.
The result of the operation is transferred to AC.

ADD to AC:
This instruction adds the
content of the memory
word specified by the
effective address to the value of AC. The sum is transferred into AC and the output carry Cout is
transferred to the E (extended accumulator) flip-flop.

LDA: Load to AC
1. This instruction transfers the memory word specified by the
effective address to AC.
2. The microoperations needed to execute this instruction are
STA: Store AC
1. This instruction stores the content of AC into the memory word specified by the effective
address.
2. Since the output of AC is applied to the bus and the data input of memory is connected to the
bus,
BUN: Branch Unconditionally
1. This instruction transfers the program to the instruction specified by the effective address.
2. The BUN instruction allows the programmer to
specify an instruction out of sequence and we say
that the program branches (or jumps) unconditionally.

BSA: Branch and Save Return Address

1. This instruction is useful for branching to a portion of the program called a subroutine or
procedure.
2. When executed, the BSA instruction stores the address of the next instruction in sequence
(which is available in PC) into a memory location specified by the effective address.
3. The effective address plus one is then transferred
to PC to serve as the address of the first instruction
in the subroutine.

A numerical example that

demonstrates how this instruction is
used with a subroutine is shown in
fig

1. The BSA instruction is

assumed to be in memory at
address 20.
2. The I bit is 0 and the address
part of the instruction has the
binary equivalent of 135.
3. After the fetch and decode
phases, PC contains 21, which is the address of the next instruction in the program
(referred to as the return address). AR holds the effective address 135.
4. This is shown in part (a) of the figure.
5. The BSA instruction performs the following numerical operation:

1. The result of this operation is shown in part (b) of the figure.

2. The return address21 is stored in memory location 135 and control continues with the
subroutine program starting from address 136.
3. The return to the original program (at address 21) is accomplished by means of an
indirect BUN instruction placed at the end of the subroutine.
4. When this instruction is executed, control goes to the indirect phase to read the effective
address at location 135, where it finds the previously saved address 21.
5. When the BUN instruction is executed, the effective address 21 is transferred to PC.
6. The next instruction cycle finds PC with the value 21, so control continues to execute
the instruction at the return address.
7. The BSA instruction must be executed with a sequence of two microoperations:
ISZ: Increment and Skip if Zero
1. This instruction increment the word specified by the effective address, and if the
incremented value is equal to 0, PC is incremented by 1 to skip the next instruction in
the program.
2. Since it is not possible to increment a word inside the memory, it is necessary to read
the word into DR, increment DR, and store the word back into memory.

Control Flowchart
A flowchart showing all microoperations for the execution of the seven memory-reference
instructions is shown in Fig.
The control functions are indicated on top
of each box.

• The microoperations that are

performed during time T4, T5, or
T6 depend on the operation code
value. This is indicated in the
flowchart by six different paths, one
of which the control takes after the
instruction is decoded.

• The sequence counter SC is

cleared to 0 with the last timing
signal in each case.

• This causes a transfer of

control to timing signal T0 to start
the next instruction cycle.

Note that we need only seven timing signals to execute the longest instruction (ISZ).
The computer can be designed with a 3-bit sequence counter. The reason for using a
4-bit counter for SC is to provide additional timing signals for other instructions that
are presented in the problems section.

Register-Reference Instructions:
1. Register-reference instructions are recognized by the control when D7 = 1 and I=0.
2. These instructions use bits 0 through 11 of the instruction code to specify one of
12instructions.
3. These 12 bits are available in IR (0-11).
4. These instructions are executed with the clock transition associated with timing variable
T3.
5. Control function needs the Boolean relation D7I’T3, which we designate for
convenience by the symbol r.
6. By assigning the symbol Bi to bit i of IR, all control functions can be simply denoted
by rBi.
 7. For example, the instruction CLA has the hexadecimal code 7800, which gives the binary
equivalent 0111 1000 0000 0000. The first bit is a zero and is equivalent to I ’ .
8. The next three bits constitute the operation code and are recognized from decoder output D7.
9. Bit 11 in IR is 1 and is recognized from B11. The control function that initiates the
microoperation for this instruction is D7I’T3 B11 = rB11.
10. The execution of a register-reference instruction is completed at time T3.
11. The sequence counter SC is cleared to 0 and the control goes back to fetch the next instruction
with timing signal T0.
12. The first seven register-reference instructions perform clear, complement, circular shift, and
increment microoperations on the AC or E registers.
13. The next four instructions cause a skip of the next instruction in sequence when a stated
condition is satisfied. The skipping of the instruction is achieved by incrementing PC once
again.
14. The condition control statements must be recognized as part of the control conditions.
15. The AC is positive when the sign bit in AC(15) = 0; it is negative when AC(15) = 1. The content
of AC is zero (AC = 0) if all the flip-flops of the register are zero.
16. The HLT instruction clears a start-stop flip-flop S and stops the sequence counter from
counting.

Input-Output and Interrupt:

Instructions and data stored in memory must come from some input device.
1. Computational results must be transmitted to the user through some output device.
2. To demonstrate the most basic requirements for input and output communication, we
will use as an illustration a terminal unit with a keyboard and printer.

Input-Output Configuration:
1. The terminal sends and receives serial information. Each quantity of information has
eight bits of an alphanumeric code.
2. The serial information from the keyboard is shifted into the input register INPR.
3. The serial information for the printer is stored in the output register OUTR.
4. These two registers communicate with a communication interface serially and with
the AC in parallel. The input-output configuration is shown in Fig. below. The
transmitter interface receives serial information from the keyboard and transmits it to
INPR.
 5. The receiver interface receives information from OUTR and sends it to the printer
serially.

6. The input register INPR consists of eight bits and holds an alphanumeric input information.
The 1-bit input flag FGI is a control flip-flop. The flag bit is set to 1 when new information is
available in the input device and is cleared to 0 when the information is accepted by the
computer.
7. The flag is needed to synchronize the timing rate difference between the input device and the
computer.
8. The process of information transfer is as follows. Initially, the input flag FGI is cleared to 0.
When a key is struck in the keyboard, an 8-bit alphanumeric code is shifted into INPR and the
input flag FGI is set to 1.
9. As long as the flag is set, the information in INPR cannot be changed by striking another key.
The computer checks the flag bit; if it is 1, the information from INPR is transferred in parallel
into AC and FGI is cleared to 0. Once the flag is cleared, new information can be shifted into
INPR by striking another key.

Input and output Instructions

1. Input and
output
instructions
are needed
for
transferring
information
to and from AC register, for checking the flag bits, and for controlling the interrupt
facility.
2. Input-output instructions have an operation code 1111 and are recognized by the control
when D7 = 1 and I = 1.
3. The remaining bits of the instruction specify the particular operation.
4. These instructions are executed with the clock transition associated with timing signal
T3.
5. Each control function needs a Boolean relation D7IT3, which we designate for
convenience by the symbol p.
6. The control function is distinguished by one of the bits in IR (6-11).
7. By assigning the symbol Bi to bit i of IR, all control functions can be denoted by pBi
for i = 6 though 11.
8. The sequence counter SC is cleared to 0 when p = D7IT3 = 1.
9. The last two instructions set and clear an interrupt enable flip-flop IEN.
Program Input
1. The computer keeps checking the flag bit, and when it finds it set, it initiates an
information transfer. The difference of information flow rate between the computer
and that of the input—output device makes this type of transfer inefficient.
2. An alternative to the programmed controlled procedure is to let the external device
inform the computer when it is ready for the transfer.
3. In the meantime the computer can be busy with other tasks. This type of transfer uses
the interrupt facility.
4. While the computer is running a program, it does not check the flags.
5. When a flag is set, the computer is momentarily interrupted from the current program.
6. The computer deviates momentarily from what it is doing to perform of the input or
output transfer. It then returns to the current program to continue what it was doing
before the interrupt.
7. The interrupt enable flip-flop IEN can be set and cleared with two instructions.
• When IEN is cleared to 0 (with the IOF instruction), the flags cannot interrupt
the computer.
• When IEN is set to 1(with the ION instruction), the computer can be interrupted
The way that the interrupt is handled by the computer can be explained by means of the
flowchart of Fig.
1. An interrupt flip-flop R is included
in the computer. When R = 0, the
computer goes through an
instruction cycle.
2. During the execute phase of the
instruction cycle IEN is checked
by the control.
3. If it is 0, it indicates that the
programmer does not want to use
the interrupt, so control continues
with the next instruction cycle.
4. If IEN is 1, control checks the flag
bits. If both flags are 0, it indicates
that neither the input nor the output
registers are ready for transfer of
information. In this case, control
continues with the next instruction
cycle.
5. If either flag is set to 1 while IEN = 1, flip-flop R is set to 1. At the end of the execute
phase, control checks the value of R, and if it is equal to 1, it goes to an interrupt cycle
instead of an instruction cycle

Interrupt cycle:
1. The interrupt cycle is a hardware implementation of a branch and save return address
operation.
2. The return address available in PC is stored in a specific location.
3. This location may be a processor register, a memory stack, or a specific memory
location.
4. An example that shows what happens during the interrupt cycle is shown in Fig.
5. When an interrupt occurs and R is set to 1 while the control is executing the instruction
at address 255.
6. At this time, the returns address 256 is in PC.
7. The programmer has previously placed an input—output service program in memory
starting from address 1120 and a BUN 1120 instruction at address 1. This is shown in
Fig. a.
8. When control reaches timing signal T0 and finds that R = 1, it proceeds with the
interrupt cycle.
9. The content of PC (256) is stored in memory location 0, PC is set to 1, and R is cleared
to 0.
10. The branch instruction at address 1 causes the program to transfer to the input—output
service program at address 1120.
11. This program checks the flags, determines which flag is set, and then transfers the
required input or output information.
12. Once this is done, the instruction ION is executed to set IEN to 1 (to enable further
interrupts), and the program returns to the location where it was interrupted.