PD INPUTS

PNR :
• Inputs :
• Gate-Level Netlist (.v)
• Timing Libraries (.lib)
• Constraint file (.sdc)
• Physical Libraries (.lef)
• Technology files (techlef / .tf )
• RC coefficient File (TLU+)
• Power specification file (UPF)
• Multi mode Multi corner file (MMMC file)
• Design exchange format (.Def) & Scan Def (Scandef)
Gate-Level Netlist (.v) :
• A gate-level netlist in VLSI (Very-Large-Scale Integration) is a textual representation of an
electronic circuit after the synthesis stage of the VLSI design flow. It describes the circuit in terms
of:
• Standard Cells (Logic Gates): Instances of basic logic gates like AND, OR, NOT, NAND, NOR, XOR,
XNOR, as well as sequential elements like flip-flops and latches. These cells are taken from a
standard cell library provided by the technology vendor
• Interconnections (Nets): The electrical connections between the input and output pins of these
standard cells. Each net represents a set of pins that are electrically connected.
• Key Characteristics of a Gate-Level Netlist:
• Low Level of Abstraction: It's a structural description close to the physical implementation of the
circuit. It specifies exactly which gates are used and how they are connected.
• Output of Synthesis: The gate-level netlist is the primary output of the logic synthesis process.
Synthesis tools take a high-level hardware description and translate it into an optimized network
of logic gates that can implement the desired functionality while meeting specified constraints
(like timing, power, and area).
• Machine-Readable Format: It's typically stored in a text-based format that can be easily parsed
and processed by Electronic Design Automation (EDA) tools. Common formats include Verilog
netlist, VHDL netlist, and EDIF (Electronic Data Interchange Format)
Timing Libraries (.lib) :
• In VLSI, files with the extension .LIB refer to timing libraries, also known as Liberty files. These are
ASCII files that contain crucial information about the standard cells and macro blocks used in a
digital circuit design. They are essential for various stages of the VLSI design flow, particularly for
synthesis and static timing analysis (STA).
• .Lib files contains :
• Timing Information:
• Cell Delays: Specifies the time it takes for a signal to propagate through a cell from an input pin to
an output pin. These delays are often characterized as look-up tables that depend on:
• Input Transition Time (Slew): The rate at which the input signal changes.
• Output Load Capacitance: The capacitive load connected to the output pin.
• Operating Conditions (PVT): Process, Voltage, and Temperature variations. Different files are often
provided for different PVT corners (e.g., worst-case, best-case, typical).
• Timing Constraints: Define the timing requirements for sequential elements like flip-flops and
latches, including:
• Setup Time: The minimum time a data signal must be stable before the clock edge.
• Hold Time: The minimum time a data signal must remain stable after the clock edge.
• Removal Time: The minimum time the asynchronous reset or set signal must be inactive before the
clock edge
• Recovery Time: The minimum time the asynchronous reset or set signal must be inactive after the
clock edge.
• Minimum Pulse Width: The minimum duration for which a clock or reset signal must be high or low.
• Timing Arcs: Define the input-output paths within a cell for which timing information is provided.
• Timing Sense (Unateness): Indicates whether the output transition is in the same direction (positive
unate) or opposite direction (negative unate) as the input transition.
• Power Information:
• Cell Power: Specifies the power consumed by the cell under different operating conditions and
input/output states. This can include
• Static Power (Leakage Power): Power consumed when the cell is not switching.
• Dynamic Power (Switching Power): Power consumed due to the charging and discharging of
capacitances during signal transitions. This often depends on switching frequency and output load.
• Power Dissipation Models: Define how power consumption varies with input patterns, output load,
and other factors.
• Physical Information :
• Cell Area: The area occupied by the standard cell on the silicon die. This is important for area
estimation during synthesis and placement.
• Pin Information: Details about each pin of the cell, including: Direction: Input, output, or inout.
• Capacitance: The input capacitance of an input pin or the output capacitance of an output pin.
• Function: The logical function associated with the pin (e.g., data input, clock input, output).
• Related Pins: For timing arcs, specifies the related input and output pins.
• Operating Conditions and Units:
• Defines the units used for time, voltage, current, power, and capacitance within the library.
• Specifies the nominal, minimum, and maximum values for process, voltage, and temperature.
• Library and Technology Names: Identifies the library and the technology node for which it is
characterized.
• In the VLSI Design Flow:
• Synthesis: Synthesis tools use the files to estimate the delay and power of different logic
implementations of the RTL design. They choose the standard cells from the library that meet the
design constraints (timing, power, area).
• Static Timing Analysis (STA): STA tools use the detailed timing information in the .lib files to verify
that the circuit meets all specified timing requirements. They calculate the delays through various
paths in the circuit and check for setup and hold time violations.
• Power Analysis: Power analysis tools use the power information in the .lib files to estimate the
power consumption of the design at different stages.
• In summary .lib files are a fundamental part of the VLSI design ecosystem, providing a
standardized way to represent the timing, power, and basic physical characteristics of standard
cells and macro blocks. They enable EDA tools to make accurate estimations and perform critical
analyses throughout the design flow. They are usually provided by the semiconductor foundries
or standard cell library vendors.
Constraints file (.sdc) :
• The Constraints File (SDC - Synopsys Design Constraints) in VLSI is a crucial ASCII file (typically with
a .sdc extension that specifies the design intent to various Electronic Design Automation (EDA)
tools involved in the VLSI design flow, such as synthesis, place and route (PNR), and static timing
analysis (STA). It essentially tells the tools what the desired behavior and performance of the
circuit should be.
• SDC file contains :
• Timing Constraints: These are the most critical part of the SDC file, defining the speed and
synchronization requirements of the design.
• Clock Definitions: Specifies the characteristics of all clock signals in the design, including ,
• Create_clock : Defines the primary clock sources, their period, waveform (rise and fall times), and
the ports or pins they are connected to.
• Create_generated_clock : Defines clocks that are derived from other clocks within the design
(e.g., through clock dividers or multipliers). It specifies the source clock and the relationship (e.g.,
divide-by, multiply-by, inversion).
• Create_virtual_clock : Defines clocks that exist in the environment interacting with the chip but
are not physically present on the chip itself. Useful for constraining input and output delays.
• Set_clock_latency : Specifies the delay from the clock source to the clock pin of a sequential
element. This can be broken down into source latency (delay from the ideal clock source to the
clock root) and network latency (delay from the clock root to the clock pin).
• Set_clock_uncertainity : Accounts for variations in the clock signal, such as jitter and skew, which
can affect setup and hold time margins.
• Set_clock_transition : Specifies the rise and fall times of the clock signal at the clock pins of
sequential elements.
• Input and Output Delays: Define the timing relationship between the external environment and
the chip's input and output ports.
• Set_input_delay : Specifies the time at which an input signal arrives at a port relative to an
external clock edge.
• Set_output_delay : Specifies the time required for a signal to propagate from an output port to
an external capturing element relative to an internal clock edge.
• Timing Exceptions: These commands override the default timing analysis for specific paths or
conditions.
• Set_false_path : Identifies paths that should not be analyzed for timing violations because they
are functionally irrelevant or operate under different conditions.
• Set_multicycle_path : Specifies paths that take more than one clock cycle for data to propagate
reliably.
• Design Rule Constraints: These specify physical limitations imposed by the manufacturing
process.
• Set_max_transition : Limits the maximum rise or fall time of a signal on a net or port to ensure
signal integrity.
• Set_max_capacitance : Limits the maximum capacitive load on a net or output port to prevent
excessive delays.
• Set_max_fanout : Limits the maximum number of loads that a cell's output can drive to maintain
signal integrity and performance.
• Area Constraints: These guide the synthesis and PNR tools to meet area targets.
• Set_max_area : Specifies the maximum allowable area for the synthesized or placed design.
• Power Constraints : These are used in low-power designs.
• Commands related to power domains, voltage levels, and power optimization techniques (often
defined in a separate UPF or CPF file, but can be referenced or have basic settings in SDC).
• In the VLSI Design Flow :
• Synthesis: The synthesis tool reads the SDC file to understand the timing, area, and power goals.
It then tries to map the RTL design onto the standard cell library in a way that meets these
constraints.
• Placement and Routing (PNR): The PNR tools use the SDC file, especially the timing constraints,
to guide the placement of cells and the routing of interconnections to achieve the desired timing
performance.
• Static Timing Analysis (STA): The STA tool uses the SDC file to verify that the final layout meets all
the specified timing requirements under various operating conditions.
• In summary the SDC file acts as a contract between the designer and the EDA tools, ensuring that
the final silicon implementation meets the functional and performance specifications of the
design. A well-written SDC file is crucial for achieving timing closure and a successful VLSI design.
Physical libraries (.lef ) :
• In VLSI Physical Design (PD), physical libraries are essential sets of files that provide the EDA
(Electronic Design Automation) tools with the necessary physical information about the standard
cells, macro blocks (like memories and IP blocks), and the technology process itself. These libraries
guide the tools during placement, routing, and physical verification stages
• Library Exchange Format (LEF) Files (.lef) :
• LEF files are ASCII-based and describe the physical abstractions of standard cells and macro blocks.
They provide essential information for placement and routing without revealing the detailed layout.
• Cell (Macro) LEF: Contains the abstract view of each standard cell and macro block, including
• Cell Name and Class: Identifies the cell and its type (e.g., CORE, PAD).
• Origin and Size: The reference point and dimensions (width and height) of the cell
• Symmetry: Allowed orientations (e.g., X, Y, XY, R0, R90, R180, R270).
• Pin Information: Pin name, direction (input, output, inout), and use (signal, clock, power, ground).
• Pin shape and layer.
• Pin location
• Pin Capacitance
• Importance in Physical Design:
• Physical libraries are indispensable for:
• Placement: The LEF files provide the dimensions and pin locations of cells, allowing the
placement tools to arrange them optimally within the chip area while considering design rules.
• Routing: The LEF and technology files define the available routing layers, their properties, and the
design rules that must be followed when connecting the cells.
• Physical Verification: The technology files contain the detailed design rules that are checked
during layout verification (DRC - Design Rule Checking) to ensure the layout is manufacturable.
• Parasitic Extraction: The technology files provide the models needed to estimate the resistance
and capacitance (parasitics) of the interconnects, which are crucial for accurate timing analysis
(STA) after routing.
• In summary, physical libraries in VLSI PD act as the fundamental blueprint for the physical
implementation of an integrated circuit, providing the essential information about the building
blocks and the manufacturing process to the EDA tools.
Technology files (tech lef / .tf )
• The technology file in VLSI Physical Design (PD) is a crucial input file that contains information specific to
the semiconductor manufacturing process being used. It acts as a bridge between the design and the
fabrication teams, enabling the EDA tools to generate a layout that adheres to the foundry's rules and
capabilities.
• Technology files typically contain a wide range of information, including but not limited to:
• Layer Definitions:
• Names and numbers of different layers used in the process (e.g., metal layers like METAL1, METAL2, via
layers like VIA1, VIA2, polysilicon, diffusion).
• Visual properties like color and pattern for layout viewing .
• Type and direction of each routing layer (horizontal or vertical preference).
• Physical and Electrical Characteristics of Layers and Vias :
• Dimensions: Minimum and maximum width and height of features on each layer.
• Spacing Rules: Minimum allowed spacing between features on the same or different layers.
• Pitch: Preferred distance between centers of repetitive features.
• Resistance: Resistance per unit length or per square for conductive layers.
• Capacitance: Capacitance per unit area or per unit length between different layers.
• Maximum Current Density: Limits on the current that can flow through a given width of a metal layer.
• Via Information: Dimensions, layers connected, and spacing rules for vias.
• Manufacturing Grid:
• The resolution or the smallest unit on which the layout features must be aligned.
• Placement Site Definitions:
• Defines the basic grid for placing standard cells, including their size and orientation constraints.
• Design Rules (DRC): A comprehensive set of rules that the layout must satisfy to be
manufacturable (e.g., minimum enclosure of contacts by metal, minimum overlap of layers).
• Units and Precision: Defines the units used for length, capacitance, resistance, voltage, current,
and time within the file.
• Formats of Technology Files:
• The format of technology files can vary depending on the EDA tool vendor. Some common
formats include:
• .tf: Used by Synopsys tools.
• .techlef: A format based on the LEF syntax, often used by Cadence tools.
• In the VLSI Physical Design Flow:
• The technology file is one of the most critical input files for the physical design stage. It is used by
all the major PD tools:
• Floorplanning: To understand the basic dimensions and constraints of the technology.
• Placement: To place standard cells and macros according to the placement grid and design rules.
• Routing: To define the available routing layers, their properties, and the rules for connecting
different components.
• Physical Verification (DRC): To check if the final layout adheres to all the manufacturing rules
defined in the technology file.
• Parasitic Extraction: To provide the models for calculating the resistance and capacitance of the
interconnects based on the layer properties and geometries.
• In conclusion, technology files are the foundational link between the logical design and the
physical realization of a VLSI chip. They contain the essential manufacturing process information
that guides and constrains all steps of the physical design flow, ultimately ensuring a successful
and manufacturable integrated circuit.
RC coefficient File (TLU+) :
• In VLSI Physical Design (PD), an RC coefficient file contains information about the resistance (R) and
capacitance (C) characteristics of the interconnects (wires and vias) used to connect the various
components (standard cells, macro blocks) in an integrated circuit. This file is crucial for accurately
estimating the delays introduced by these interconnects, which significantly impact the overall timing
and performance of the chip, especially at advanced technology nodes.
• Here's a breakdown of what you need to know about RC coefficient files in VLSI PD:
• The RC coefficient file typically contains the following information for each metal and via layer in the
technology:
• Resistance per Unit Length: Specifies the resistance per unit length (e.g., ohms per micron) for
horizontal and vertical segments on each metal layer.
• Capacitance per Unit Length: Specifies the capacitance per unit length (e.g., farads per micron) for:
• Area Capacitance: Capacitance between the metal layer and the layers above and below it.
• Coupling Capacitance: Specifies the capacitance between adjacent parallel metal lines on the same or
different layers as a function of their spacing.
• Via Resistance and Capacitance: Specifies the resistance and capacitance associated with each type of
via connecting different metal layers.
• Process-Specific Parameters: The file may also include parameters that account for advanced process
effects like wire width and spacing variations, and dielectric properties.
• The format of RC coefficient files can vary depending on the EDA tool vendor and the foundry.
Some common types include:
• TLU+ (Table Look-Up Plus): This is a binary format used by Synopsys tools. It's a table-based model
that provides RC values based on wire width, spacing, and layer information, offering high
accuracy and runtime efficiency. It often includes minimum and maximum TLU+ files to represent
process variations. A map file is used to link the technology file layer names with the TLU+ file.
• ITF (Interconnect Technology Format): This is another format, and TLU+ files are often generated
from ITF files.
• QRC Techfile / Cap Table: Used by Cadence's QRC (Quantus QRC Extraction) tool.
• Input to Extraction Tools: The RC coefficient file is a primary input to parasitic extraction tools
(e.g., Synopsys StarRC, Cadence Quantus QRC).
• Parasitic Extraction: The extraction tool analyzes the physical layout (typically in DEF format) and,
using the RC coefficient file, calculates the parasitic resistances and capacitances of all the
interconnects in the design.
• SPEF Output: The extraction tool generates a Standard Parasitic Exchange Format (SPEF) file,
which contains a detailed netlist with the extracted RC parasitics for each net.
• Timing and Signal Integrity Analysis: The SPEF file is then used by STA and signal integrity analysis
tools to perform accurate simulations and verification.
• In VLSI Physical Design (PD), a power specification file defines the power intent of the design,
especially in systems with multiple power domains, power gating, voltage scaling, and other low-
power techniques. This file is crucial for EDA tools to understand how power is managed within
the chip during various operating modes.
• UPF (Unified Power Format):
• UPF describes the power intent at a relatively high level, allowing for specification, simulation,
and verification of low-power designs.
• UPF Contains :
• Power Domains: Definition of different voltage areas within the chip, specifying which logic
belongs to which domain.
• Power Supplies: Description of the power and ground networks, including their names and
connectivity to power domains.
• Power States: Specification of different operating modes of the chip or individual power domains
(e.g., ON, OFF, Standby, Sleep) and the voltage levels associated with them.
• Power Switches: Definition of power gating structures used to turn off power to specific domains,
including the control signals.
• Isolation Strategies: Rules for isolating signals crossing between power domains with different
voltage levels or when one domain is powered down (e.g., using isolation cells)
• Level Shifters: Specification of level shifters needed for signals crossing between power domains
operating at different voltage levels.
• Retention Strategies: Mechanisms to preserve the state of memory elements (registers,
memories) when a power domain is turned off (e.g., using retention registers with a backup
power supply).
• Power Modes: Definition of legal combinations of power states for different power domains.
• Supply Nets and Ports: Explicit definition of power and ground nets and the ports they connect
to.
• Connectivity Rules: Specification of how power and ground are connected to different cells and
blocks.
• In summary, the power specification file (typically in UPF or CPF format) is a vital input in modern
VLSI physical design, especially for low-power designs. It communicates the intended power
management architecture to the EDA tools, enabling them to implement and verify the design
correctly with respect to its power behavior.
Multi-Mode-Multi-corner file (MMMC) :

• In VLSI Physical Design (PD), an MMMC file is not a standard file format like LEF, DEF, or SDC.
Instead, MMMC stands for Multi-Mode Multi-Corner, and it refers to a methodology and a setup
used during various stages of the design flow, especially Static Timing Analysis (STA) and Physical
Implementation (Place and Route).
• The purpose of MMMC is to ensure that the chip design functions correctly and meets its
performance requirements across various operating conditions and manufacturing variations.
These variations can significantly affect the timing and power characteristics of the integrated
circuit.
• Instead of a single "mmmc file," the MMMC setup involves creating and managing multiple views
of the design based on different combinations of:
• Modes: These represent different functional or operational states of the chip. A chip might have
different modes like:
• Functional Mode: The normal operating mode of the chip.
• Test Mode (Scan, ATPG): Modes used for testing the manufactured chip.
• Low Power Modes (Sleep, Standby): Modes where the chip consumes less power.
• Each mode can have its own set of active clocks, operating voltages, and specific timing
constraints (SDC files).
• Corners: These represent different Process, Voltage, and Temperature (PVT) conditions and
manufacturing variations. Corners are crucial because transistor behavior and interconnect
characteristics change with these variations. Common corners include:
• Process Corners: Variations in the manufacturing process that affect transistor speed (e.g., Fast-
Fast (FF), Slow-Slow (SS), Fast-Slow (FS), Slow-Fast (SF), Typical-Typical (TT)).
• Voltage Corners: Variations in the power supply voltage (e.g., nominal, high, low).
• Temperature Corners: Variations in the operating temperature (e.g., high, low, typical).
• Interconnect Corners (RC Corners): Variations in the resistance and capacitance of the
interconnects due to manufacturing process variations (e.g., maximum capacitance, minimum
capacitance, maximum RC, minimum RC, typical RC).
• the MMMC setup is typically defined and managed within the EDA tools (like Synopsys Innovus,
Cadence Genus/Innovus, Siemens EDA Calibre). This involves:
• Specifying Timing Libraries (.libs): Different .lib files are provided by the foundry for each process
and PVT corner, characterizing the delay and power of standard cells under those conditions.
• Providing Constraint Files (.sdc): Different SDC files might be used for different operating modes,
reflecting the specific timing requirements for each mode (e.g., different clock frequencies or
interface timings).
• Defining RC Coefficient Files/Tables: These files (like TLU+ in Synopsys or QRC techfiles in
Cadence) model the interconnect resistance and capacitance variations across different process
corners.
• Configuring the EDA Tool: The user specifies the different modes and corners to be considered in
the analysis. This is usually done through Tcl scripts or GUI interfaces within the EDA tool. The tool
then creates different analysis views based on all the relevant combinations of modes and
corners.
• MMMC is a methodology for considering multiple operating modes and
manufacturing/environmental variations during design and analysis. This is achieved by providing
the EDA tools with the necessary library, constraint, and RC information for each mode and
corner, and then configuring the tool to analyze the design across all relevant combinations.
Design exchange format (Def) :
• The Design Exchange Format (DEF) is a crucial ASCII file format used in the physical design (PD)
stage of the VLSI (Very Large Scale Integration) design flow. It serves as a standard way to
represent the physical layout of an integrated circuit and facilitates the exchange of design data
between different Electronic Design Automation (EDA) tools.
• Think of a DEF file as a detailed blueprint of your chip after the logical design (represented by a
netlist) has been synthesized. It describes the "where" and "how" of the components on the
silicon.
• A DEF file typically includes the following information :
• Header: Contains version information, units of measurement, and design name.
• Components: Lists all the instances of cells (standard cells, macros, IP blocks) used in the design
• Pins: Describes the I/O pins of the design, including their:
• Nets: Specifies the electrical connections (netlist) between the pins of the components and I/O
ports.
• Routes (Optional): May contain detailed routing information, describing the physical paths of the
wires connecting the nets, including:
• Die Area: Defines the boundaries of the silicon die.
• Core Area: Specifies the area within the die where the active circuitry (standard cells and macros)
is placed.
• Rows : Describes the rows used for standard cell placement.
• Tracks : Defines the routing tracks available on the different metal layers
• Blockages: Specifies areas where placement or routing is restricted.
• Role of DEF in VLSI Physical Design:
• Data Exchange: The primary purpose of DEF is to facilitate the transfer of the physical layout
information between different stages and tools in the physical design flow. For example, the
output of the placement stage (a DEF file with placed components) is used as input for the
routing stage.
• Implementation : Place and route (P&R) tools generate and consume DEF files to understand the
component placement and connectivity requirements for routing.
• Analysis and Verification: Post-layout analysis tools (for timing, power, signal integrity) and physical
verification tools (DRC, LVS) use DEF files to analyze the physical implementation.
• ECO (Engineering Change Order): Modifications to the design after initial layout are often captured
and implemented using DEF files.
• Tapeout : While the final layout is typically in GDSII format, DEF files can represent the design at various
stages leading up to tapeout.
• In summary, the Design Exchange Format (DEF) is a fundamental file format in VLSI physical
design that captures the physical layout of the integrated circuit, enabling seamless data
exchange and facilitating the various stages of implementation, analysis, and verification.
 Scan-def :

• Scan Chain Definition: This is the core information describing the structure and connectivity of the
scan chains. It specifies:
• The number of scan chains: How many independent scan chains are implemented in the design
• The flip-flops belonging to each scan chain: A list of all the sequential elements
(specifically, the scan flip-flops) that are part of each scan chain.
• The order of flip-flops within each scan chain: The serial connection sequence from the scan-in (SI)
port to the scan-out (SO) port for each chain. This is critical for correctly shifting test data.
• The scan-in (SI) and scan-out (SO) for each chain: The primary input and output pins on
the chip dedicated to each scan chain.
• The scan enable (SE) signal(s): The control signal(s) that put the flip-flops into scan mode.
• Clock domain information: Which clock domain each scan chain (or segments of it)
belongs to. This is important for clock balancing and timing analysis.
• How PD Tools Utilize Scan Definition Inputs:
• Placement: Ensuring that the scan flip-flops belonging to the same chain are placed in a
way that facilitates efficient routing of the scan chain connections. The tool might try to
keep them relatively close to minimize wire lengths
• Routing: Connecting the scan-out of one flip-flop to the scan-in of the next in the specified
order. The router needs to understand the dedicated scan nets and ensure they are
routed correctly, often with specific routing rules.
• Clock Tree Synthesis (CTS): Handling the clock signals for the scan flip-flops, especially if
they belong to different clock domains. The scan enable signal also needs to be routed
appropriately.
• Timing Analysis: Performing timing analysis on the scan chains, considering the setup and
hold times for the scan-in and scan-out signals during test mode.
• Optimization: Performing scan chain reordering to improve routing congestion, wire
length, and timing. This involves changing the order of flip-flops within a chain while
maintaining the logical functionality.
• DFT Rule Checks: Verifying that the scan chains are implemented correctly and meet the DFT
requirements.
• Scan-def inputs provide the physical design tools with the necessary blueprint of the scan
architecture so that they can correctly implement it in the physical layout while meeting
performance, area, and testability goals. Without this information, the PD tools would not know
which flip-flops form the scan chains or how they should be connected for testing.
There are some optional files that might be required especially for block-level PnR implementation. These files are as below :

• Block partition:
• For block-level PnR, we need a defined core area for the block or block partitions which defines the size and
shape of the block. Block shape could be a simple rectangular or a complex rectilinear shape.
• Pin def :
• For block-level PnR, pin locations have been decided by the Full chip owner and for block-level, we have to
use the predecided pin location in order to match the pin locations with other blocks. Generally, it is given
in form of a def file. In case of any pin placement issue at the block level, the block owner can inform the
person who is placing the pin and if required block owner can also edit the pin placement.
• Power plan script :
• For block-level PnR, the power plan should be as per the full chip. The power plan has been decided on full
chip and in block level, the Power plan should be used as per full chip. A power plan could be given a set of
rules or a power plan script (.tcl file).
• UPF :
• The power intent file describes which power rails should be routed to individual blocks and when the block
should be powered on or shut down. Unified Power Format (.upf) and Common Power Format (.cpf) are
two different formats of power intent files. CPF format is used by the Cadence tool and UPF format by the
other tools. We must need this file if the block is having a multi-voltage domain.
Static Timing Analysis (STA) :
• The Synopsys PrimeTime tool is an industry-standard for Static Timing Analysis (STA) in VLSI. It
requires several input files to perform accurate timing verification. Here's a comprehensive list of
the inputs for PrimeTime:
• The inputs for Static Timing Analysis (STA) in VLSI are crucial for accurately verifying the timing
performance of a digital circuit. Here's a breakdown of the essential input files and information:
• Gate-Level Netlist:
• This is the circuit description after logic synthesis, detailing all the standard cells, macro blocks,
and their interconnections
• It represents the structural view of the design that STA will analyze for timing paths.
• Timing Libraries (.lib):
• These libraries, usually in Liberty format, provide the timing characteristics of all the standard
cells and macro blocks used in the netlist
• It contains :
• Cell delay (input to output propagation delay) under various input slew and output load
conditions
• Setup and hold time requirements for sequential elements
• Pin capacitances.
• Transition time (slew) derating factors.
• Operating conditions (process, voltage, temperature - PVT) for which the library is characterized
• Constraints File (SDC - Synopsys Design Constraints):
• This file, written in Tcl syntax, specifies the timing requirements and operating conditions for the
design. It's the most critical input for directing the STA tool. Key constraints include:
• Clock Definitions: Definition of all clock signals (period, waveform, duty cycle, source)
• Generated Clocks: Definition of clocks derived from primary clocks (e.g., divided or multiplied
clocks).
• Input and Output Delays: Timing constraints on the input and output ports of the design relative
to external clocks.
• Timing Exceptions: False paths, multi-cycle paths, and minimum/maximum delay constraints on
specific paths
• Parasitic Files (SPEF - Standard Parasitic Exchange Format):
• Generated after place and route, the SPEF file contains the extracted resistance and capacitance
(RC) values of the interconnects (wires and vias) in the physical layout.
• These parasitics significantly impact signal delays and are crucial for accurate post-layout STA.
Physical Verification(PV) INPUTS :
• Physical verification in VLSI ensures the correctness and manufacturability of the chip layout. It
involves several checks, each with its specific inputs:
• Design Rule Check (DRC):
• Inputs:
• Layout Database: GDSII file representing the physical layout.
• Rule Deck File: A text file provided by the foundry that specifies the design rules for the target
technology node. This file is specific to the DRC tool being used (e.g., Calibre, IC Validator)
• Technology File (LEF): Provides layer definitions and basic physical properties.
• Layout Versus Schematic (LVS):
• Inputs:
• Layout Database: GDSII file
• Schematic Netlist: A description of the intended circuit connectivity, usually in SPICE or a similar
format, generated from the schematic design.
• LVS Rule Deck: A tool-specific file that defines how to extract devices and connectivity from the
layout and compare it with the schematic netlist.
• Cell Library : Provides information about the standard cells and IP blocks used in the design
• Electrical Rule Check (ERC):
• Inputs:
• Layout Database: GDSII file
• ERC Rule Deck: A file containing rules for checking electrical connectivity and potential issues like
floating nets, shorts between power and ground, etc.
• Technology File: Provides layer and connectivity information
• Antenna Check:
• Inputs:
• Layout Database: GDSII file
• Antenna Rule File: Provided by the foundry, specifying the maximum allowed ratio of metal area
to gate area for each metal layer connected to a gate.
• Technology File: Provides layer information.
• Power Analysis (IR Drop and Electromigration - EM):
• Layout Database: GDSII file with routing information.
• Power Specification File (UPF/CPF): Defines power domains, voltage levels, and power/ground
networks.
• Current Density Rules: Specified in the technology file or a separate EM rule file from the
foundry.
• Voltage Drop Constraints: Specified by the designer.
• Activity Files (SAIF/VCD): Provide information about signal switching activity for dynamic power
analysis
• RC Extraction Files (SPEF): Contain resistance and capacitance of interconnects.
• In summary, the primary inputs for physical verification are the layout database (GDSII/OASIS)
and a set of rule decks and technology files provided by the foundry and EDA tool vendors.
Additional files like netlists, power specifications, and activity files are needed for specific
verification checks like LVS and power analysis
• STAR RC EXTRACTION :
• StarRC extraction in VLSI is the process of accurately calculating the parasitic resistance (R),
capacitance (C), and sometimes inductance (L) of the interconnects (wires and vias) in a physical
layout of an integrated circuit. Synopsys StarRC is an industry-standard tool used for this crucial
step.
• INPUTS :
• StarRC takes several input files that describe the physical layout and the technology being used.
The key inputs include:
• Layout Database: Typically in DEF (Design Exchange Format), GDSII, or OASIS format. This
describes the placement and routing of the design.
• Physical Libraries: LEF (Library Exchange Format) files for the technology and the standard
cells/macros used. These provide physical dimensions and pin locations
• RC Coefficient File (Technology File): Contains process-specific rules and parameters for calculating
resistance and capacitance. Common formats include ITF (Interconnect Technology Format) and,
for advanced nodes, TLU+ (Table Look-Up Plus) files with associated map files.
• Netlist: A gate-level netlist (e.g., in Verilog) can help ensure accurate connectivity extraction.
• StarRC extraction is a critical step that bridges the gap between the idealized schematic and the
reality of the physical implementation on silicon. By accurately quantifying the parasitic effects of
the interconnects, it enables designers to verify and optimize their designs for performance,
LOGIC EQUIVALENCE CHECK (LEC) :
• In VLSI, Logic Equivalence Checking (LEC) is a formal verification technique that ensures two
different representations of a digital circuit design are functionally equivalent. This is crucial at
various stages of the design flow, such as after synthesis, after place and route, or after ECO
(Engineering Change Order) implementation.
• INPUTS :
• Golden netlist : This is the design that is considered the correct or trusted version. It's often the
RTL (Register Transfer Level) code after functional verification or a gate-level netlist that has
already been proven correct.
• Gate level Netlist :
• This is the design that needs to be verified against the reference design. It could be:
• The gate-level netlist produced by synthesis from the RTL.
• The placed and routed netlist.
• Library Files:
• These files (.lib or .db in Liberty format) contain the functional description of the standard cells
and macro blocks used in both the reference and implemented designs. The LEC tool needs these
to understand the behavior of each component.
• SDC (Synopsys Design Constraints) files: These files specify timing constraints, clock definitions,
and other design intent. While LEC primarily focuses on functional equivalence, these constraints
can sometimes influence the synthesis and optimization process, leading to structural differences.
Providing these can help the LEC tool understand the intended behavior under specific
conditions.
• In summary, the essential inputs for LEC are the two design representations (reference and
implemented) and the libraries used to build them. Optional but helpful inputs include constraint
files and black box definitions. The LEC tool then compares the logical functionality of these two
designs to determine if they behave identically under all possible input conditions.
Sign-off :
• The "sign-off" stage in VLSI design is the final verification and approval process before sending the
design for fabrication (tape-out). It involves a comprehensive set of checks to ensure the design
meets all specifications and is manufacturability. The inputs for these sign-off checks come from
various stages of the design flow. Here's a breakdown of the key input categories and specific
files:
• Layout Database:
• GDSII or OASIS: The final physical layout of the chip, containing all the geometric information
about the different layers, cells, and interconnects.
• Netlists:
• Post-Placement and Routing Netlist (Physical Design Netlist): Describes the connectivity of the
placed and routed design
• SPEF (Standard Parasitic Exchange Format) Netlist: Contains the extracted resistance, capacitance,
and inductance (RCL) values of the interconnects from the physical layout. This is crucial for
accurate post-layout timing and signal integrity analysis.
• Gate-Level Netlist (for LEC): The synthesized netlist used as a golden reference for logical
equivalence checking.
• Libraries:
• Timing Libraries (.lib or .db): Provide detailed timing characteristics of standard cells and macro
blocks under various operating conditions (PVT)
• Physical Libraries (.lef): Describe the physical dimensions, pin locations, and routing rules for
standard cells and macro blocks.
• Technology Files: Contain detailed information about the manufacturing process, including layer
properties, design rules, and extraction parameters.
• Signal Integrity (SI) Libraries: Model noise and crosstalk characteristics of interconnects and cells.
• Power Libraries: Contain power consumption information for cells under different operating
conditions
• Constraint Files:
• SDC (Synopsys Design Constraints): Specifies timing requirements, clock definitions, operating
conditions, and exceptions for static timing analysis.
• UPF (Unified Power Format) or CPF (Common Power Format): Defines the power intent of the
design, including power domains, voltage levels, and power management strategies.
• DRC (Design Rule Check) Rule Files: Provided by the foundry, these files specify the geometric
rules that the layout must adhere to for manufacturability
• LVS (Layout Versus Schematic) Rule Files: Define how to extract the circuit from the layout and
compare it with the schematic netlist.
• Antenna Rule Files: Specify rules to prevent antenna effects during manufacturing.
• EM (Electromigration) Rule Files: Define current density limits for metal layers to ensure
reliability.
• IR Drop Analysis Setup Files: Specify power grid characteristics, current sources, and voltage drop
limits.
• The Sign-off stage requires a comprehensive set of data representing the design's logical behavior,
physical implementation, technology constraints, and operating conditions to ensure a robust and
manufacturable chip. The specific set of input files can vary slightly depending on the design
complexity, technology node, and the EDA tool flow being used.