Unit3

Gate level modelling

 Introduction
Digital designers are normally familiar with all the common logic

gates, their symbols, and their working.

Flip-flops are built from the logic gates. All other functionally

complex and more involved circuits can also be built using the
basic gates.
 All the basic gates are available as “Primitives” in Verilog.

Primitives are generalized modules that already exist in Verilog

[IEEE].
 They can be instantiated directly in other modules.
 AND Gate Primitive

 The AND gate primitive in Verilog is instantiated with the following statement:

I1
and g1 (O, I1, I2, . . ., In); O
I2
I
 Here ‘and’ is the keyword signifying an AND
n gate. g1 is the name assigned
to
the specific instantiation. O is the gate output; I1, I2, etc., are the gate inputs.
The AND module has only one output. The first port in the argument list is

the output port.

 An AND gate instantiation can take any number of inputs — the upper
limit is
compiler-specific.
 A name need not be necessarily assigned to the AND gate instantiation;
this is
Verilog Code for AND Gate Test bench for AND
Gate
module andgate (b,a1,a2); module tb;
reg a1,a2;
output b;
wire b;
input a1,a2; begin
initial a1
a1 = 0; g1 b
and g1(b,a1,a2); a2 = 0;
endmodule #100 a1 = 1; a2 And Gate Primitive
#100 a1 = 0;
#200 a2 = 1;
#400 a1 = 1;
#200 a2 = 0;
Truth Table for AND #100 a2 = 1;
Gate end
andgate g1(b, a1, a2);
initial
$monitor($time,"a1 = %b a2 = %b b = %b",
a1, a2, b);
initial #1500 $finish;
endmodule
 MODULE STRUCTURE
 The first statement of a module starts with the keyword module; it may
be
followed by the name of the module and the port list if any
 All the variables in the ports-list are to be identified as inputs, outputs,

or inouts.
The corresponding declarations have the form shown below:
 Input a1, a2;
 Output b1, b2;
 Inout c1, c2;
The port-type declarations here follow the module declaration

mentioned above.

module module_name (b1,b2,c1,c2,a1,a2);

 The ports and the other variables used within the body of the module are to
be
identified as nets or registers with specific types in each case.
 The respective declaration statements follow the port-type declaration statements.

Examples:
 wire a1, a2, c;
 reg b1, b2;
The type declaration must necessarily precede the first use of any variable

or signal in the module.

 The last statement in any module definition is the keyword “endmodule”.
 Other Gate Primitives

Basic gate primitives in Verilog with details

Rules for deciding the output values of gate primitives for different input combinations
 Examples
 The commonly used A-O-I gate is shown below.

The circuit has been realized here by instantiating the AND and

NOR gate primitives.

 The module aoi_gate in the figure has input and output ports since it

describes a circuit with signal inputs and an output.

 It generates inputs to the aoi_gate module and gets its output.
 The module aoi_st is a stimulus module (test bench)
 It has no input or output ports.
 Verilog code for
AOI
module
aoi_gate(o,a1,a2,b1,b2);
input a1,a2,b1,b2; // a1,a2,b1,b2 form the input ports of the module
output o; //o is the single output port of the module
wire o1,o2; //o1 and o2 are intermediate signals within the
module
and
g1(o1,a1,a //The AND gate primitive has two instantiations
2);
//with assigned names g1 & g2.
and g2(o2,b1,b2);
nor //The nor gate has one instantiation with assigned name
g3.
g3(o,o1,o2);
endmodule
Test bench for
AOI
Simulation time for
AOI
 2X1 MUX

Verilog for 2X1 MUX

S_c

module mux2x1(out,a,b,s,); a and_1

input a,b,s;
out
wire and_1,and_2,s_c;
output out; and_2
not (s_c,s); b

and (and_1,a,s_c);
and (and_2,b,s);
e
or (out,and_1,and_2); s
endmodule
 4X1 MUX Using 2X1 MUX

module mux4x2(out,i0,i1,i2,i3,s1,s0);
input i0,i1,i2,i3,s1,s0,; I0
output out; 2 X 1 Mux mux1
I1
wire mux1,mux2;
mux2x1 mux_1(mux1,i0,i1,s1); out
2 X 1 Mux
mux2x1 mux_2(mux2,i2,i3,s1);
mux2x1 mux_3(out,mux1,mux2,s0);
I2
endmodule mux1
2 X 1 Mux
I3 s0

s1
 16X1 MUX Using 4X1 MUX
I[0]
module mux16x1(y,i,s);
4 X 1 Mux
m1
input [16:0]i;
I[3]
input [3:0]s;
I[4]
output y;
m2
4X 1 Mux
wire y
4 X 1 Mux
m1,m2,m3, I[7]

m4; m3
I[8]
mux4x2
4 X 1 Mux
u1(m1,i[0],i
[1],i[2],i[3], I[11]
s[1],s[0]);
m4 s3
mux4x2 I[12] s2
u2(m2,i[4],i
4 X 1 Mux
[5],i[6],i[7],
s[1],s[0]); I[15]

mux4x2
u3(m3,i[8],i s1 s0
 2 to 4 Decoder

module decoder2_4(y0,y1,y2,y3,a,b,en);
input a,b,en;
output y0,y1,y2,y3;
wire aa,bb;
not(aa,a),(bb,b);
and(y0,aa,bb,en), (y1,aa,b,en), (y2,a,bb,en), (y3,a,b,en);
endmodule
 3 to 8Decoder Using 2 to 4 Decoder

module dec3_8(y0,y1,y2,y3,y4,y5,y6,y7,a,b,c);
input a,b,c;
not (c1,c);
output y0,y1,y2,y3,y4,y5,y6,y7;
decoder2_4 g1(y0,y1,y2,y3,a,b,c1);
decoder2_4 g2(y4,y5,y6,y7,a,b,c);
endmodule
 4 to 16 Decoder Using 3 to 8Decoder

module dec4_16(y,a,en);
input [3:0]a;
output [15:0]y;
input en;
wire p;
not (p,a[3]);
dec3_8
u1(y[0],y[1],y[
2],y[3],y[4],y[5
],y[6],y[7],a[0],
a[1],a[2],p);
dec3_8
u2(y[8],y[9],y[
10],y[11],y[12],
y[13],y[14],y[1
5],a[0],a[1],a[2
],a[3]);
 Tri-State Gates

bufif1 nn(out, in, control);

ARRAY OF INSTANCES OF
PRIMITIVES
The primitives available in Verilog can also be instantiated as arrays. A typical
array instantiation has the form

and gate [3 : 0 ] (a, b, c);

where a, b, and c are to be 4 bit vectors.
The above instantiation is equivalent to combining the following 4 instantiations:

and gate [3] (a[3], b[3], c[3]), gate [2] (a[2], b[2], c[2]), gate [1] (a[1],
b[1], c[0]), gate [4] (a[0], b[0], c[0]);
 Example: A Byte
Comparator
Verilog Code
module comp(d,a,b,en);
input en;
input[7:0]a,b;
output d;
C[7]
wire [7:0]c;
wire dd; C[6]

xor g1[7:0] C[0]

(c,b,a);
or(dd,c[0],c
[1],c[2],
c[3], c[4],
c[5], c[6],
c[7],);
notif1(d,dd,en); Note: g1[0]....g1[6], g1[7] are gate instantiation name
C[0]....c[6],c[7] are output of xor (considered as wire)
endmodule
Test bench for comparator

module comp_tb;
reg[7:0]a,b;
reg en;
comp gg(d,a,b,en);
initial
begin
a = 8'h00;
b=
8'h00;
en = 1'b0;
end
always
#2 en = 1'b1;
always
begin
#2 a =
a+1'b1;
#2 b =
b+2'd2;
end
initial
 Half
Adder
Test Bench
Verilog Code
module tstha();
module ha(s,ca,a,b); reg a,b;
wire s,ca;
input a,b; ha hh(s,ca,a,b);
output s,ca; initial
begin
xor(s,a,b); a=0;b=0;
and(ca,a,b); end
always
endmodule begin
#2
a=1;b
=0;
#2
a=0;b
=1;
#2
a=1;b
=1;
#2
 Full
Adder
Verilog Code

module fa(sum,cout,a,b,cin);
input a,b,cin;
output sum,cout;
wire s,c1,c2;
ha ha1(s,c1,a,b), ha2(sum,c2,s,cin);
or(cout,c2,c1);
endmodule
 Test Bench for Full Adder
module tst_fa();
reg a,b,cin;
Wire sum,car;
fa
ff(sum,cout,a,b,
cin);
initial
begin
a =0;b=0;cin=0;
end
always
begin
#2
a=1;b=1;cin=0;
#2
a=1;b=0;cin=1;
#2
a=1;b=1;cin=1;
#2
a=1;b=0;cin=0;
#2
 Verilog code for 4 x 1 Mux

module mux4_1(y,i,s);
input [3:0] i;
input [1:0] s; I[0] Yy[0]
output y;
I[1] Yy[1]
wire [1:0] ss;
wire [3:0]yy; Yy[2]
I[2]
not Yy[3]
(ss[0],s[0]), I[3]
(ss[1],s[1]);
and
(yy[0],i[0],ss
[0],ss[1]);
and
(yy[1],i[1],s[
0],ss[1]);
and
(yy[2],i[2],ss
Test bench for 4 x 1 Mux

module tst_mux4_1();
reg [3:0]i;
reg [1:0] s;
mux4_1 mm(y,i,s);
initial

begin
#2{i,s} = 6'b 0000_00;
#2{i,s} = 6'b
0001_00; #2{i,s} =
6'b 0010_01; #2{i,s}
= 6'b 0100_10;
#2{i,s} = 6'b 1000_11;
#2{i,s} = 6'b
0001_00;
end
initial
$monitor($time," input s = %b,y = %b" ,s,y);
endmodule
 Design of Flip-flops with Gate Primitives
Verilog code for Nand Latch with Test bench
Verilog code for SR Flip flop with Test bench
Verilog code for JK Flip flop with Test bench