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Lecture 2

The document provides an introduction to Verilog, a popular Hardware Description Language (HDL) used for designing and verifying digital systems. It explains the structure of Verilog modules, levels of abstraction, and details various gate-level models including instantiation of basic gates like AND, OR, and NOT. Additionally, it includes examples of Verilog code for implementing a multiplexer and adders, showcasing how to describe digital circuits using gate-level primitives.

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11 views28 pages

Lecture 2

The document provides an introduction to Verilog, a popular Hardware Description Language (HDL) used for designing and verifying digital systems. It explains the structure of Verilog modules, levels of abstraction, and details various gate-level models including instantiation of basic gates like AND, OR, and NOT. Additionally, it includes examples of Verilog code for implementing a multiplexer and adders, showcasing how to describe digital circuits using gate-level primitives.

Uploaded by

Zeeshan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Lecture 2

Prepared by: Mariyum Jamshid


Introduction
• It’s a very well known fact that Verilog is a popular HDL language used
in the Design and Verification of Digital Systems
• HDL stands for Hardware Description Language is a computer based
language that describes the hardware of a digital system(like logic
gates, multiplexers, decoder, adders, flip-flops, counters, registers,
ALU, memory etc)
• This Verilog is very much similar to high level software language “C”.
Verilog Design
Module
• Module is the basic building block of Verilog. It provides the port interfaces
and functionality of the hardware
• Every module has two parts. One is Declaration part and the other is the
Body.
• The Declaration part has the name of the module, port list and declaration
of the ports.
• The Body which is the main part pf the module represents the input, output
relations
• In Verilog, it is illegal to nest module i.e one module definition cannot
contain another module definition within the module and endmodule
statement.
Example
module name of the module(port list);
input port names;
output port names;
Body of the module
{input out relations}
endmodule
Here the most important thing “Description of the output -input
relations”
This depend on the type of model we prefer.
Level Of Abstraction
• In Verilog hardware can be defined in four levels of abstraction
depending on the need of the design
1. Behavioral or Algorithmic Level
2. Dataflow
3. Gate Level
4. Switch Level
• Among the above four level engineer prefer to use the mix of the
models, dataflow and behavioral model
Gate Level Model
• This is also known as Structural model by many.
• At this level, the design is described using basic gates and registers (or
storage elements)
• The gate level is essentially a schematic (either graphically or text-
based) that contains the components and connections that will
implement the functionality from the above levels of abstraction.
• Verilog supports basic logic gates as predefined primitives. So, this
gate level model uses the logic gates.
Gate Level Model

• These primitives are instantiated like modules except that they are
predefined in Verilog and do not need a module definition.
• These gates are instantiated to build logic circuits in Verilog
• There are two classes of basic gates:
• And/or gates
• Buf /note gates
And/Or Gate
• And / or gates have one scalar output and multiple scalar inputs.
• The first terminal in the list of gate terminals is an output and the
other terminals are inputs.
• The and/or gates available in Verilog are :
• Here the output terminal is denoted by out. Input terminals are
denoted by i1 and i2
• These gates are instantiated to build logic circuits in Verilog.
• Here the simple meaning of instantiation is invoking or calling.
1. and a1 (out,i1,i2);
2. nand na1 (out,i1,i2);
3. or or1 (out,i1,i2);
4. nor nor1 (out,i1,i2);
5. xor xor1 (out,i1,i2);
6. xnor xnor1 (out,i1,i2);
Buf/Not Gate
• Similarly Verilog also provides two basic buf/ not gate primitives.
• The symbol for these logic gates are shown below
Gate Instantiation of Buf/Not Gates
• // basic gate instantiations
• buf b1 (out,in);
• not n1 (out,in);
• //more than two outputs
• buf b1_2out (o1,o2,i);
• // gate instantiation without instance name
• not (o,i);
Example: X-Or Gate
• The output Y of X-or gate with A, B inputs is
Y=A’.B+ A.B’
• According to gate level modeling , it can be described using primitives
gate s as shown below
Gate Level Verilog Code
module xorgate(Y,A,B);
input A,B;
output Y;
wire A’,B’ ,C,D; // intermediate connection
not NOT1(A’,A);
not NOT2 (B’,B);
and AND1 (C,A’,B);
and AND2 (D,A,B’);
or OR (Y,C,D);
endmodule
Gate Level Design of Multiplexor
(MUX)
• Below diagram denotes a 2:1 MUX in terms of basic logic gates like
And, Or, Not etc.
• A & B are inputs and A1, B1 are intermediate inputs to or gate. Hence
they are declared as ‘wire’. The output is
Gate Level Design of Multiplexor
(MUX)
• The block diagram of 2:1 MUX is shown below.
Gate level Verilog code for 2:1 MUX
module mymux2_1(A,B,S,Y);
//Port declaration
output y;
input A,B,S;
//internal variable declarations
wire S1,A1,B1;
not n1 (S1,S);
and a1 (A1,A,S1);
and a2 (B1,B,S);
or o1(Y,A1,B1);
endmodule
Gate Level Half-Added
• A half adder adds two binary numbers and outputs as sum & carry as
shown below.

• Hear a, b are inputs s and c are outputs.


• This Half adder can be designed at the Gate level using one XOR gate, one
and gate as shown in the diagram.
Gate level model-HA
• From the diagram it is clear that, the half adder is designed using one
x-or gate and one and gate.
• The output of x-or gate gives the half sum and the output of and gate
gives carry.
Verilog code for HA
module myHA1(S,C,A,B);
input A,B;
output S,C;
xor XOR1(S,A,B); //Instantiations of X-OR gate
and AND1(C,A,B); //Instantiations of AND gate
endmodule
Full Adder – Gate Level Model
• Full adder adds has three input bits and two output bits sum and
carry out as shown in the diagram below
• In the diagram A,B,C in are inputs and Sum & Cout are outputs
Gate levels Schematic - FA
• The design uses two x-or gates, 3 AND gates and one OR-gate as
shown in the schematic.
Gate level Verilog Code for FA
module myFA1(S,Cout,A,B,Cin);
//Port declaration
output S,Cout;
input A,B,Cin;
//internal variable declaration
wire D,E,F,G;
xor X-OR1(D,A,B);
xor X-OR2(S,D,Cin);
and AND1(E,A,Cin);
and AND2(F,Cin,B);
and AND3(G,A,B);
or OR1(Cout,E,F,G);
endmodule
Exercise
• Implement the following truth table using gate level primitive.
• Lets call the design systemX and implements its logic as a canonical
SOP logical expression.
Solution

1. F=ΣA,B,C (0,2,6)=A’B’C’+A’BC’+ABC’
2. The corresponding logic diagram is as follows:
Code:
module System X (F, A,B,C);
output F;
input A,B,C;
wire An,Bn,Cn; // internal nets
wire mo,m2,m6;
not U0 (An,A); //Not’s
not U1 (Bn,B);
not U2 (Cn,C);
and U3(m0,An,Bn,Cn); //And’s
and U4(m2,An,B,Cn);
and U5(m6,A,B,Cn);
or U6 (F,m0,m2,m6); //Or
endmodule

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