RISC-V Processor Datapath

Recap: Complete RV32I ISA

Not in this course

2
 State Required by RV32I ISA
Each instruction reads and updates this state during execution:
• Registers (x0..x31)
− Register file (or regfile) Reg holds 32 registers x 32 bits/register: Reg[0].. Reg[31]
− First register read specified by rs1 field in instruction
− Second register read specified by rs2 field in instruction
− Write register (destination) specified by rd field in instruction
− x0 is always 0 (writes to Reg[0]are ignored)
• Program Counter (PC)
− Holds address of current instruction
• Memory (MEM)
− Holds both instructions & data, in one 32-bit byte-addressed memory space
− We’ll use separate memories for instructions (IMEM) and data (DMEM)
▪ Later we’ll replace these with instruction and data caches
− Instructions are read (fetched) from instruction memory (assume IMEM read-only)
− Load/store instructions access data memory
4/10/2020 3
 One-Instruction-Per-Cycle RISC-V Machine
• On every tick of the clock,
the computer executes one
instruction
pc • Current state outputs drive
the inputs to the
combinational logic, whose
clock outputs settles at the
IMEM values of the state before
Combinational the next clock edge
Logic
• At the rising clock edge, all
Reg[]
the state elements are
updated with the
combinational logic
outputs, and execution
DMEM moves to the next clock
cycle
CS 61c 4
 Basic Phases of Instruction Execution

rd

Reg[]
PC

IMEM
rs1

DMEM
ALU
rs2

+4 imm
mux

1. Instruction 2. Decode/ 5. Register

3. Execute 4. Memory
Fetch Register Write
Read
Clock
4/10/2020 time 5
 Implementing the add instruction

add rd, rs1, rs2

• Instruction makes two changes to machine’s state:
− Reg[rd] = Reg[rs1] + Reg[rs2]
− PC = PC + 4

CS 61c 6
 Datapath for add
+4 Reg[]
DataD Reg[rs1]
pc
pc+4
IMEM
inst[11:7]
AddrD
inst[19:15] AddrA DataA Reg[rs2]
+ alu

inst[24:20] AddrB DataB

inst[31:0] RegWriteEnable
(RegWEn)
Control Logic
CS 61c 7
 Timing Diagram for add
+4 Reg[]
DataD Reg[rs1]
pc
pc+4 IMEM inst[11:7] AddrD
inst[19:15]AddrA DataA Reg[rs2]
+ alu
inst[24:20]AddrB DataB
inst[31:0]
RegWEn
clock time
Clock

PC 1000 1004
PC+4 1004 1008

inst[31:0] add x1,x2,x3 add x6,x7,x9

Reg[rs1] Reg[2] Reg[7]

Reg[rs2] Reg[3] Reg[9]

alu Reg[2]+Reg[3] Reg[7]+Reg[9]

Reg[1] ??? Reg[2]+Reg[3] 8

 Implementing the sub instruction

sub rd, rs1, rs2

• Almost the same as add, except now have to subtract
operands instead of adding them
• inst[30] selects between add and subtract

CS 61c 9
 Datapath for add/sub
+4 Reg[]
DataD Reg[rs1]
ALU
pc IMEM
inst[11:7]
AddrD alu
pc+4 inst[19:15] AddrA DataA Reg[rs2]
inst[24:20] AddrB DataB

inst[31:0] RegWEn ALUSel

(1=write, 0=no write) (Add=0/Sub=1)
Control Logic
CS 61c 10
 Implementing other R-Format instructions

• All implemented by decoding funct3 and funct7 fields and

selecting appropriate ALU function
CS 61c 11
Implementing the addi instruction
• RISC-V Assembly Instruction:
addi x15,x1,-50

111111001110 00001 000 01111 0010011

imm=-50 rs1=1 ADD rd=15 OP-Imm

4/10/2020 12
 Datapath for add/sub
+4 Reg[]
DataD Reg[rs1]
ALU
pc IMEM
inst[11:7]
AddrD alu
pc+4 inst[19:15] AddrA DataA Reg[rs2]
inst[24:20] AddrB DataB

inst[31:0] RegWEn ALUSel

(1=write, 0=no write) (Add=0/Sub=1)
Control Logic
CS 61c 13
 Adding addi to datapath
+4 Reg[]
DataD
ALU
pc IMEM
inst[11:7]
AddrD Reg[rs1] alu
pc+4 inst[19:15] AddrA DataA 0
inst[24:20] AddrB DataB
Reg[rs2] 1

inst[31:20]
Imm. imm[31:0]
Gen

inst[31:0] ImmSel=I RegWEn=1 BSel=1 ALUSel=Add

Control Logic
CS 61c 14
 I-Format immediates

inst[31:0]

------inst[31]-(sign-extension)------- inst[30:20]

imm[31:0]
inst[31:20] imm[31:0]
Imm.
Gen • High 12 bits of instruction (inst[31:20]) copied to low 12 bits
of immediate (imm[11:0])
ImmSel=I • Immediate is sign-extended by copying value of inst[31] to
fill the upper 20 bits of the immediate value (imm[31:12])
CS 61c 15
 Adding addi to datapath
+4 Reg[]
DataD
ALU
pc IMEM
inst[11:7]
AddrD Reg[rs1] alu
pc+4 inst[19:15] AddrA DataA 0
inst[24:20] AddrB DataB
Reg[rs2] 1
Also works for all other I-
inst[31:20]
format arithmetic instruction
Imm. imm[31:0] (slti,sltiu,andi,ori,
Gen xori,slli,srli,srai)
just by changing ALUSel
inst[31:0] ImmSel=I RegWEn=1 BSel=1 ALUSel=Add

Control Logic
CS 61c 16
Implementing Load Word instruction
• RISC-V Assembly Instruction:
lw x14, 8(x2)

000000001000 00010 010 01110 0000011

imm=+8 rs1=2 LW rd=14 LOAD

4/10/2020 17
 Adding addi to datapath
+4 Reg[]
DataD
ALU
pc IMEM
inst[11:7]
AddrD Reg[rs1] alu
pc+4 inst[19:15] AddrA DataA 0
inst[24:20] AddrB DataB
Reg[rs2] 1

inst[31:20]
Imm. imm[31:0]
Gen

inst[31:0] ImmSel=I RegWEn=1 BSel=1 ALUSel=Add

Control Logic
CS 61c 18
 Adding lw to datapath
alu
+4 Reg[]
wb
DataD Reg[rs1] ALU 1
pc inst[11:7] AddrD
DMEM
IMEM Reg[rs2] Addr DataR
wb
pc+4 inst[19:15] AddrA DataA 0 0
mem
inst[24:20] AddrB DataB 1

inst[31:20]
Imm. imm[31:0]
Gen

inst[31:0] ImmSel RegWEn BSel ALUSel MemRW WBSel

CS 61c 19
 Adding lw to datapath
alu
+4 Reg[]
wb
DataD Reg[rs1] ALU 1
pc inst[11:7] AddrD
DMEM
IMEM Reg[rs2] Addr DataR
wb
pc+4 inst[19:15] AddrA DataA 0 0
mem
inst[24:20] AddrB DataB 1

inst[31:20]
Imm. imm[31:0]
Gen

inst[31:0] ImmSel=I RegWEn=1 Bsel=1 ALUSel=Add MemRW=Read WBSel=0

CS 61c 20
 All RV32 Load Instructions

funct3 field encodes size and

signedness of load data

• Supporting the narrower loads requires additional circuits to

extract the correct byte/halfword from the value loaded from
memory, and sign- or zero-extend the result to 32 bits before
writing back to register file.
21
Implementing Store Word instruction
• RISC-V Assembly Instruction:
sw x14, 8(x2)

0000000 01110 00010 010 01000 0100011

offset[11:5] rs2=14 rs1=2 SW offset[4:0] STORE
=0 =8

4/10/2020 0000000 01000 combined 12-bit offset = 8 22

 Adding lw to datapath
alu
+4 Reg[]
wb
DataD Reg[rs1] ALU 1
pc inst[11:7] AddrD
DMEM
IMEM Reg[rs2] Addr DataR
wb
pc+4 inst[19:15] AddrA DataA 0 0
mem
inst[24:20] AddrB DataB 1

inst[31:20]
Imm. imm[31:0]
Gen

inst[31:0] ImmSel RegWEn BSel ALUSel MemRW WBSel

CS 61c 23
 Adding sw to datapath
+4 Reg[] alu
wb
DataD Reg[rs1] ALU DMEM
pc IMEM inst[11:7] AddrD 1
pc+4 Reg[rs2] Addr wb
0 DataR 0
inst[19:15] AddrA DataA
DataW mem
inst[24:20] AddrB DataB 1

inst[31:7]
Imm. imm[31:0]
Gen

inst[31:0] ImmSel RegWEn Bsel ALUSel MemRW WBSel=

CS 61c 24
 Adding sw to datapath
+4 Reg[] alu
wb
DataD Reg[rs1] ALU DMEM
pc IMEM inst[11:7] AddrD 1
pc+4 Reg[rs2] Addr wb
0 DataR 0
inst[19:15] AddrA DataA
DataW mem
inst[24:20] AddrB DataB 1

inst[31:7]
Imm. imm[31:0]
Gen

inst[31:0] ImmSel=S RegWEn=0 Bsel=1 ALUSel=Add MemRW=Write WBSel=*

*= “Don’t Care”

CS 61c 25
 I-Format immediates

inst[31:0]

------inst[31]-(sign-extension)------- inst[30:20]

imm[31:0]
inst[31:20] imm[31:0]
Imm.
Gen • High 12 bits of instruction (inst[31:20]) copied to low 12 bits
of immediate (imm[11:0])
ImmSel=I • Immediate is sign-extended by copying value of inst[31] to
fill the upper 20 bits of the immediate value (imm[31:12])
CS 61c 26
 I & S Immediate Generator
inst[31:0]
31 25 24 20 19 15 14 12 11 7 6 0
imm[11:0] rs1 funct3 rd I-opcode
imm[11:5] rs2 rs1 funct3 imm[4:0] S-opcode

5
5
1 6
I S

inst[31](sign-extension) inst[30:25] inst[24:20] I

inst[31](sign-extension) inst[30:25] inst[11:7] S
31 11 10 5 4 0
• Just need a 5-bit mux to select between two positions where low imm[31:0]
five bits of immediate can reside in instruction
CS 61c 27
• Other bits in immediate are wired to fixed positions in instruction
 Implementing Branches

• B-format is mostly same as S-Format, with two

register sources (rs1/rs2) and a 12-bit immediate
• But now immediate represents values -4096 to +4094
in 2-byte increments
• The 12 immediate bits encode even 13-bit signed byte
offsets (lowest bit of offset is always zero, so no need
to store it) 28
 Adding sw to datapath
+4 Reg[] alu
wb
DataD Reg[rs1] ALU DMEM
pc IMEM inst[11:7] AddrD 1
pc+4 Reg[rs2] Addr wb
0 DataR 0
inst[19:15] AddrA DataA
DataW mem
inst[24:20] AddrB DataB 1

inst[31:7]
Imm. imm[31:0]
Gen

inst[31:0] ImmSel RegWEn Bsel ALUSel MemRW WBSel=

CS 61c 29
 Adding branches to datapath
+4 Reg[] pc alu
wb 1
DataD Reg[rs1]
alu 1 ALU
pc inst[11:7] AddrD 0 DMEM 1
pc+4
0 IMEM Reg[rs2] Addr DataR
wb
inst[19:15] AddrA DataA Branch 0 0
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7]
Imm. imm[31:0]
Gen

PCSel inst[31:0] ImmSel RegWEn BrUn BrEq BrLT BSel ASel ALUSel MemRW WBSel

CS 61c 30
 Adding branches to datapath
alu +4 Reg[] pc alu
wb 1
DataD Reg[rs1]
1 ALU
pc inst[11:7] AddrD 0 DMEM 1
0 IMEM Reg[rs2] Addr DataR
wb
pc+4 inst[19:15] AddrA DataA Branch 0 0
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7]
Imm. imm[31:0]
Gen

PCSel=taken/not-taken inst[31:0] ImmSel=B RegWEn=0 BrUn BrEq BrLT Bsel=1 ASel=1 MemRW=Read WBSel=*

ALUSel=Add

CS 61c 31
 Branch Comparator
A Branch
• BrEq = 1, if A=B
B
Comp. • BrLT = 1, if A < B
• BrUn =1 selects unsigned comparison
for BrLT, 0=signed

• BGE branch: A >= B, if !(A<B)

BrUn BrEq BrLT

CS 61c 32
Multiply Branch Immediates by Shift?
• 12-bit immediate encodes PC-relative offset of -4096 to +4094 bytes in multiples of 2
bytes
• Standard approach: treat immediate as in range -2048..+2047, then shift left by 1 bit to
multiply by 2 for branches
s imm[10:5] rs2 rs1 funct3 imm[4:0] B-opcode

sign-extension s imm[10:5] imm[4:0] S-Immediate

sign-extension s imm[10:5] imm[4:0] 0 B-Immediate (shift left by 1)

Each instruction immediate bit can appear in one of two places in output immediate value –
so need one 2-way mux per bit

CS 61c 33
 RISC-V Branch Immediates
• 12-bit immediate encodes PC-relative offset of -4096 to +4094 bytes in multiples of 2
bytes
• RISC-V approach: keep 11 immediate bits in fixed position in output value, and rotate
LSB of S-format to be bit 12 of B-format

sign=imm[11] imm[10:5] imm[4:0] S-Immediate

sign=imm[12] imm[10:5] imm[4:1] 0 B-Immediate (shift left by 1)

imm[11]

Only one bit changes position between S and B, so only need a single-bit 2-way mux

CS 61c 34
 RISC-V Immediate Encoding
Instruction Encodings, inst[31:0]

32-bit immediates produced, imm[31:0]

Only bit 7 of instruction changes role in

Upper bits sign-extended from inst[31] always immediate between S and B 35
Implementing JALR Instruction (I-Format)

• JALR rd, rs, immediate

− Writes PC+4 to Reg[rd] (return address)
− Sets PC = Reg[rs1] + immediate
− Uses same immediates as arithmetic and loads
▪ no multiplication by 2 bytes

36
 Adding branches to datapath
+4 Reg[] pc alu
wb 1
DataD Reg[rs1]
alu 1 ALU
pc inst[11:7] AddrD 0 DMEM 1
pc+4
0 IMEM Reg[rs2] Addr DataR
wb
inst[19:15] AddrA DataA Branch 0 0
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7]
Imm. imm[31:0]
Gen

PCSel inst[31:0] ImmSel RegWEn BrUn BrEq BrLT BSel ASel ALUSel MemRW WBSel

CS 61c 37
 Adding jalr to datapath
pc+4
+4 Reg[] pc alu
wb 1
DataD Reg[rs1] 2
alu 1 ALU
pc inst[11:7] AddrD 0 DMEM 1
pc+4
0 IMEM Reg[rs2] Addr DataR
wb
inst[19:15] AddrA DataA Branch 0 0
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7]
Imm. imm[31:0]
Gen

PCSel inst[31:0] ImmSel RegWEn BrUn BrEq BrLT BSel ASel ALUSel MemRW WBSel

CS 61c 38
 Adding jalr to datapath
pc+4
alu +4 Reg[] pc alu
wb 1
DataD Reg[rs1] 2
1 ALU
pc inst[11:7] AddrD 0 DMEM 1
pc+4
0 IMEM Reg[rs2] Addr DataR
wb
inst[19:15] AddrA DataA Branch 0 0
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7]
Imm. imm[31:0]
Gen

inst[31:0] WBSel=2
PCSel ImmSel=B RegWEn=1 Bsel=1 Asel=0 MemRW=Read
ALUSel=Add
BrUn=* BrEq=* BrLT=*

CS 61c 39
 Implementing jal Instruction

• JAL saves PC+4 in Reg[rd] (the return address)

• Set PC = PC + offset (PC-relative jump)
• Target somewhere within ±219 locations, 2 bytes apart
− ±218 32-bit instructions
• Immediate encoding optimized similarly to branch
instruction to reduce hardware cost
40
 Adding jal to datapath
pc+4
+4 Reg[] pc alu
wb 1
DataD Reg[rs1] 2
alu 1 ALU
pc inst[11:7] AddrD 0 DMEM 1
pc+4
0 IMEM Reg[rs2] Addr DataR
wb
inst[19:15] AddrA DataA Branch 0 0
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7]
Imm. imm[31:0]
Gen

PCSel inst[31:0] ImmSel RegWEn BrUn BrEq BrLT BSel ASel ALUSel MemRW WBSel

CS 61c 41
 Adding jal to datapath
pc+4
alu +4 Reg[] pc alu
wb 1
DataD Reg[rs1] 2
1 ALU
pc inst[11:7] AddrD 0 DMEM 1
pc+4
0 IMEM Reg[rs2] Addr DataR
wb
inst[19:15] AddrA DataA Branch 0 0
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7]
Imm. imm[31:0]
Gen

inst[31:0] WBSel=2
PCSel ImmSel=J RegWEn=1 Bsel=1 Asel=1 MemRW=Read
ALUSel=Add
BrUn=* BrEq=* BrLT=*

CS 61c 42
 Single-Cycle RISC-V RV32I Datapath
pc+4
+4 Reg[] pc alu
wb 1
DataD Reg[rs1] 2
alu 1 ALU
pc inst[11:7] AddrD 0 DMEM 1
pc+4
0 IMEM Reg[rs2] Addr DataR
wb
inst[19:15] AddrA DataA Branch 0 0
Comp. DataW mem
inst[24:20] AddrB DataB 1

inst[31:7]
Imm. imm[31:0]
Gen

PCSel inst[31:0] ImmSel RegWEn BrUn BrEq BrLT BSel ASel ALUSel MemRW WBSel

CS 61c 43
 And in Conclusion, …
• Universal datapath
− Capable of executing all RISC-V instructions in one cycle each
− Not all units (hardware) used by all instructions
• 5 Phases of execution
− IF, ID, EX, MEM, WB
− Not all instructions are active in all phases
• Controller specifies how to execute instructions
− what new instructions can be added with just most control?
CS 61c 44