Digital design

Ch 4. Combinational logic

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 4- 1 Combinational circuits
Logic circuits for digital system: combinational or sequential
Sequential circuits: need storage elements in addition to logic gates

Outputs from the inputs and the state of the storage
elements (previous inputs): Chapter 5-9

• Outputs are determined from the present

combination inputs
• Consist of input/ output variables and logic
gates

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 4- 2 Analysis procedure
• To determine the function of circuit
• Analysis procedure
• Make sure the circuit is combinational or
sequential
(Combinational: no feedback paths or memory elements)
• Obtain the output Boolean functions or the
truth table
To obtain the output Boolean functions from a logic diagram
Boolean function
1.Label all gate outputs as a function of input variables
2.Make output functions at each level
3.Substitute final outputs to input variables

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 Obtain procedure

Truth table
• Put the input variables to binary numbers
- For n inputs, form the 2n possible input
combinations and list the binary numbers
from 0 to 2n- 1 in a table
• Determine the output value at each gate
• Obtain truth table

F2=AB+AC+BC,T1=A+B+C
T2=ABC, T3=F2'T1, F1=T3+T2

F1=T3+T2=F2'T1+ABC=(AB+AC+BC)'(A+B+C)+ABC
= (A'+B')(A'+C')(B'+C')(A+B+C)+ABC= (A'+B'C')(AB'+AC' +BC'+B' C)+ABC
= A'BC'+A'B'C+AB'C' +ABC 4
 4- 3 Design procedure
• Procedure to design
- From the specifications of the circuit,
determine the required number of input and
output from specification
- Assign a letter symbol to each input/ output
- Derive the truth table
- Obtain the simplified Boolean functions
- Draw the logic diagram and verify design
correctness

Output binary functions in the truth table are simplified
by algebraic manipulation, map method, computer-
based simplification
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 Code conversion example
• BCD to excess- 3 code converter
- Excess- 3 code: decimal digit+3
• Design procedure
1)Determine inputs/ outputs
Inputs: A,B,C,D (0000∼1001)
Outputs: W,X,Y,Z (0011∼1100)

2)Derive truth table

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 Code converter example
3)Obtain simplified Boolean functions

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 Code converter example
4)Draw the logic diagram

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 4- 4 Binary adder- subtractor
• Binary adder
- Half adder: performs the addition of 2- bits(x+y)

0+0=0, 0+1=1, 1+0=1, 1+1=10
(Higher significant bit of this result: carry)
- Full adder: performs the addition of 3- bits(x+y+z)
- Two half adder can be employed to a full adder

• Realization of Binary adder- subtractor

- Half adder
- Full adder
- Cascade of n- full adder
- Providing a complementing circuit

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 Half Adder
• Sum of 2 binary inputs
• Input: x(augend), y(addend) S=xy′+x′y
Output: S(sum), C(carry) C=xy

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 Full adder
• Sum of 3 binary inputs
• Input : x,y(2 significant bits), z(1 carry bit)
• Output : S(sum), C(carry)

S=z+(x+y) = z'(xy'+x'y)+z(xy'+x'y)'
= z'(xy'+x'y)+z(xy+x'y') = xy'z'+x'yz'+xyz+x'y'z
C=z(xy'+x'y)+xy=xy'z+x'yz+xy 11
Full adder

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 Binary adder
• Sum of two n- bit binary numbers
- 4- bit adder
A=1011, B=0011

Most significant bit Least significant bit

C3 has to wait for C2 and so on down to C1 and C0

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 Carry propagation
The longest propagation delay time in an adder is the time it takes
the carry to propagate through the full adder

• Rising of delay time (carry delay)

• One solution is carry lookahead
• All carry is a function of Pi,Gi and C0

Pi=Ai+Bi: carry propagate (associated with the propagation of the carry from Ci to Ci+1
Gi=AiBi: carry generate (produce a carry of 1 both Ai and Bi are 1, regardless of the input
carry Ci
Carry if both of (Ai and Bi) =1
Si=Pi+Ci, Ci+1=Gi+PiCi Carry if Ci =1 and one of (Ai and Bi) =1 14
 Carry propagation
• Carry lookahead generator

C3 does not have to wait for C2 and C1

to propagate; C3 is propagated at the same
time as C1 and C2

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 Carry propagation
• 4- bit adder with carry lookahead

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 Binary subtractor
For unsigned number, A-B if A≥B, the 2’s complement of (B-A) if A < B
For signed number, A-B if there is no overflow
• A- B equals A+(2'complement of B)
• When M=0(act as adder) M=1(subtractor)
B+0=B

B+1=B'
C0=1

2'complement
of B

Results of such addition or subtraction differently,

depending on whether it is assumed that the numbers are
signed or unsigned

For singed numbers, overflow detecting

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V=1 (overflow)
(n+1)th bit is the actual sign and has been shifted out of position
 Overflow
The detection of an overflow after the addition of two binary number depends
on whether the numbers are considered to be signed or unsigned
Addition of two unsigned numbers
overflow from end carry out of MSB position
Addition of two signed numbers
end carry out of MSB position is not overflow
Sign bit
• Sum of n digit number occupies n +1digit
• Occurs when two numbers are same sign
(examples of overflow)
An overflow cannot occur after an addition of one number is positive and the
other is negative, since adding a positive number to a negative number
produces a result which is smaller than the larger of the two original numbers
positive
Carry out sign bit

Different
(exclusive- OR)
positive
overflow

negative Carry into sign bit

Overflow (exceeds the capacity of an 8 bit resister)

The answer cannot be accommodated within 8 bits
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Signed 8 bit  +127 ~ - 128
 4- 5 Decimal adder
• Calculate binary and represent decimal in binary coded form
• Decimal adder for the BCD code
For 4 bit BCD adder
Nine inputs, five outputs
Two decimal digit + carry = 9+9+1=19 (maximum)
To find a rule by which the binary sum is be converted to the correct BCD
digit representation of the number in the BCD sum
4 bit binary adder

Correction
Z8Z2=1 1010 ~ 1111
Z8Z4=1

K=1
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 BCD Adder
• BCD digit output of 2- BCD
digit sum
• Carry arise if output 1010
~ 1111
• C=K+Z8Z4+Z8Z2

1100 1010
1101 1011
1110
1111 0110

When C=1, it is necessary to add 0110

to the binary sum and provide an output carry
for the next stage

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 4- 6 Binary multiplier
• 2 bit x 2 bit = 4 bit(max) Least significant bit of the product does
Not have to go through an adder since
It is formed by the output of the first AND gate

Multiplicand is multiplied by each bit of the

multiplier starting from the least significant bit
The multiplication of two bits such as A0 and B0
produces a 1 if both bits are 1; otherwise, it
produces a 0
 AND operation
The two bit partial products are added with two half adder (HA) circuit
More bit partial products
full adders

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 Binary multiplier

• (K- bit) x (J- bit)

- (K x J) AND gates,
(J- 1) K- bit adder needed

B3B2B1B0
x A2A1A0

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 4- 7 Magnitude comparator
• Xi=1only if the pair of bits in
i are equal
- (A=B)=x3x2x1x0
- (A >B)=A3B3′+x3A2B2′+x3x2A1B1′
+x3x2x1A0B0′
- (A<B)=A3′B3+x3A2′B2+x3x2A1′B1
+x3x2x1A0′B0

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 4- 8 Decoders
• Generate the 2ⁿ(or less) minterms of n input
variables
Eg)3 to 8 line decoder

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 Decoders
• 2 to 4 line decoder with Enable input
- Control circuit operation by E

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 Decoders
• Decoders with enable inputs can be a larger
decoder circuit
Eg) 4 x16 decoder by
two 3 x 8 decoders

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 Decoders
• Combinational logic implementation
- Any combinational circuit can be implemented with line
decoder and OR gates
Eg)full adder

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 4- 9 Encoders
• Inverse operation of a decoder
• Generate n outputs of 2ⁿ input values
Eg) octal to binary encoder

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 Priority encoder
• Problem happens two or more inputs equal to 1 at the
same time
• Give a priority function to circuit

(x100 means 0100, 1100)

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 4- 10 Multiplexers
• Select a binary information from many input lines
• Selection is controlled by a set of selection lines
• 2ⁿ input lines have n selection lines

Multiplexers
• 4 to 1 line multiplexer

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 Multiplexers

• Quadruple 2 to 1
line multiplexer

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 Multiplexers

• Boolean function implementation

• Minterms of function are generated in a MUX
• n input variables, n- 1 selection input

F=xy+yz′+x′y′z 32
 Multiplexers

• Three- state gates

• Logic 1, 0 and high-
high- impedance
• High-- impedance behaves like an open circuit
High

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 Multiplexers

• Multiplexers with three- state gates

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 4- 11 HDL for combinational circuit

• Modeling techniques:
• Gate level modeling
 Instantiation of gates and user defined modules
• Dataflow modeling
statements assign
 Using continuous assignment statements-
• Behavioral modeling
statements always
 Using procedural assignment statements-

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 Gate- level modeling
• Circuit is specified by its gates and their
interconnection

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 Instantiation

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Instantiation in 4- bit adder

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 Dataflow modeling

• Assign a value to a
net by using
operands and
operators
eg)J=01,K=10 can be
{ J,K} =0110

out=x ? A : B means
out=A, if x is true
=B, if x is false

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 Assignment
• 2- to- 4 line decoder

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4- bit adder

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 Behavioral modeling

• Use procedural assignment

statement, always
• Target output
must be the reg
data type

Eg)4 to 1 line mux

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 Writing a simple test bench

• Test bench : Applying stimulus to test HDL

and observe its response
• reg - inputs , wire - outputs

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 System tasks

• System tasks : keywords that can display

various outputs (begin with $)
• $display , $write , $monitor , $time , $finish
• Format of system tasks
• Task name(format specification,argument list);
• Eg) $monitor(%d %b %b, C,A,B);

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Example of testbench

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