Dr. N.G.P.

Institute of Technology - Coimbatore-48

(An Autonomous Institution)

22UEE408 MICROPROCESSOR
AND MICROCONTROLLER

Uint 1 – The 8086 Microprocessor And Bus Structure

 Agenda
• Introduction to 8086

• Microprocessor Architecture

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 Introduction to 8086
• Evolution of Microprocessors
1st Gen 2nd Gen 3rd Gen
1971-1972 1973-1978 1979-1980
4-bit microprocesssor 8-bit microprocesssor 16-bit microprocesssor

5th Gen 4th Gen

1995 to till now 1981-1995
64-bit microprocesssor 32-bit microprocesssor

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 Introduction to 8086
• 1st Generation:
• Size : 4-bit
Number of
Name Year of Invention Clock speed transistors Inst. per sec

1971 by Ted Hoff

INTEL 4004/4040 and Stanley 740 kHz 2300 60,000
Mazor

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 Introduction to 8086
• 2nd Generation:
• Size : 8-bit
Number of
Name Year of Invention Clock speed transistors Inst. per sec

8008 1972 500 kHz 3500 50,000

10 times faster
8080 1974 2 MHz 6000 than 8008

1976 (16-bit
8085 address bus) 3 MHz 6500 769230

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 Introduction to 8086
• 3rd Generation:
• Size : 16-bit
Number of
Name Year of Invention Clock speed transistors Inst. per sec

1978 (multiply and

divide instruction, 4.77 MHz, 8 MHz,
8086 29000 2.5 Million
16-bit data bus and 10 MHz
20-bit address bus)

1979 (cheaper
8088 version of 8086 and 2.5 Million
8-bit external bus)

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 Introduction to 8086
• 3rd Generation:
• Size : 16-bit
Name Year of Invention Clock speed Number of transistors Inst. per sec

1982 (80188 cheaper version of

80186, and additional
80186/80188 components like interrupt 6 MHz
controller, clock generator, local
bus controller, counters)

1982 (data bus 16bit and

80286 8 MHz 134000 4 Million
address bus 24 bit)

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 Introduction to 8086
• 4th Generation:
• Size : 32-bit
Number of
Name Year of Invention Clock speed Inst. per sec
transistors
1986 (other versions 80386DX, 80386SX,
INTEL 80386 80386SL , and data bus 32-bit address bus 16 MHz – 33 275000
32 bit) MHz

INTEL 80486 1986 (other versions 80486DX, 80486SX, 16 MHz – 100 1.2 Million 8 KB of cache
80486DX2, 80486DX4) MHz transistors memory

Cache memory 8
PENTIUM 1993 66 MHz bit for instructions
8 bit for data

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 Introduction to 8086
• 5th Generation:
• Size : 64-bit
Number of
Name Year of Invention Clock speed Inst. per sec
transistors
64 KB of L1 cache
NTEL core 2 2006 (other versions core2 duo, core2 quad, 1.2 GHz to 3 291 Million per core 4 MB of L2
core2 extreme) GHz transistors cache

2.2GHz –
3.3GHz, 2.4GHz
i3, i5, i7 2007, 2009, 2010 – 3.6GHz,
2.93GHz –
3.33GHz

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 The 8086 Processor
8085 Microprocessor 8086 Microprocessor
It is an 8-bit microprocessor. It is a 16-bit microprocessor.
It has a 16-bit address line. It has a 20-bit address line.
It has a 8-bit data bus. It has a 16-bit data bus.
The memory capacity is 64 KB. The memory capacity is 1 MB.
The Clock speed of this microprocessor is 3 MHz. The Clock speed of this microprocessor varies
between 5, 8 and 10 MHz for different versions.
8085 microprocessor does not support memory 8086 microprocessor supports memory
segmentation. segmentation.
It does not support pipelining. It supports pipelining.
It has no minimum or maximum mode. It has minimum and maximum modes.
In 8085, only one processor is used. In 8086, more than one processor is used. An
additional external processor can also be employed.

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 Microprocessor Architecture –
Pin Config.

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MCQ

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 Microprocessor Architecture – CPU
Architecture

Address / Data

(20 points)

Control

(16 points)

5v
Gnd
Clk
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 Microprocessor Architecture –
Functional Units
MP

Bus Interface
Execution Unit
Unit

General
Pointers and Segment
Purpose External Bus
Index Registers Registers
Register

Instruction
Flag Registers
Queue
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 Microprocessor Architecture – CPU
Architecture
Data Group Pointer Group Segment Group

Data Registers Pointers Segment

Registers
AX AH AL SP
BX BH BL BP CS
CX CH CL SI SS
DX DH DL DI DS

IP ES
16-BIT 8-BIT 8-BIT

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 Microprocessor Architecture – Flag
Register
Conditional Flag Control Flag

Carry Flag
Aux Flag Directional
Parity Flag Interrupt
Sign Flag Trap
Zero Flag
Overflow flag

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 8086 Signals

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• AD0-AD15: Address/Data bus. These are low order address
bus. They are multiplexed with data. When AD lines are used to
transmit memory address the symbol A is used instead of AD,
for example A0-A15. When data are transmitted over AD lines
the symbol D is used in place of AD, for example D0-D7, D8-
D15 or D0-D15.
• A16-A19: High order address bus. These are multiplexed with
status signals.
• S2, S1, S0: Status pins. These pins are active during T4, T1
and T2 states and is returned to passive state (1,1,1 during T3
or Tw (when ready is inactive). These are used by the 8288 bus
controller for generating all the memory and I/O operation)
access control signals. Any change in S2, S1, S0 during T4
indicates the beginning of a bus cycle.
• A16/S3, A17/S4, A18/S5, A19/S6 : The specified address
lines are multiplexed with corresponding status signals.
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 S2 S1 S0 Characteristics

0 0 0 Interrupt
acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive state

A17/S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

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• HE’/S7: Bus High Enable/Status. During T1 it is low. It is used to enable data onto
the most significant half of data bus, D8-D15. 8-bit device connected to upper
half of the data bus use BHE (Active Low) signal. It is multiplexed with status
signal S7. S7 signal is available during T2, T3 and T4.
• RD’: This is used for read operation. It is an output signal. It is active when low.
• READY : This is the acknowledgement from the memory or slow device that they
have completed the data transfer. The signal made available by the devices is
synchronized by the 8284A clock generator to provide ready input to the
microprocessor. The signal is active high(1).
• INTR : Interrupt Request. This is triggered input. This is sampled during the last
clock cycles of each instruction for determining the availability of the request. If
any interrupt request is found pending, the processor enters the interrupt
acknowledge cycle. This can be internally masked after resulting the interrupt
enable flag. This signal is active high(1) and has been synchronized internally.

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• NMI : Non maskable interrupt. This is an edge triggered input which results in a
type II interrupt. A subroutine is then vectored through an interrupt vector lookup
table which is located in the system memory. NMI is non-maskable internally by
software. A transition made from low(0) to high(1) initiates the interrupt at the end
of the current instruction. This input has been synchronized internally.
• INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each
interrupt acknowledge cycle.
• MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor
will operate in.
• RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters
used to force the microprocessor to release the local bus at the end of the
microprocessor’s current bus cycle. Each of the pin is bi-directional. RQ’/GT0′ have
higher priority than RQ’/GT1′.
• LOCK’ : Its an active low pin. It indicates that other system bus masters have not
been allowed to gain control of the system bus while LOCK’ is active low(0). The
LOCK signal will be active until the completion of the next instruction.
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• TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0),
execution will continue, else the processor remains in an idle state. The input is
internally synchronized during each of the clock cycle on leading edge of the
clock.
• CLK : Clock Input. The clock input provides the basic timing for processing
operation and bus control activity. Its an asymmetric square wave with a 33%
duty cycle.
• RESET : This pin requires the microprocessor to terminate its present activity
immediately. The signal must be active high(1) for at least four clock cycles.
• Vcc : Power Supply( +5V D.C.)
• GND : Ground

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 QS1 QS0 Status

0 0 No operation

0 1 First byte of op code from

queue

1 0 Empty the queue

1 1 Subsequent byte from queue

QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086
instruction queue according to the table shown
M/IO’: This signal is used to distinguish between memory and I/O operations.
The M Signal is Active high whereas the IO’ Signal is Active Low. When this Pin
is High, the memory operations takes place. On the other hand, when the Pin is
low, the Input/Output operations from the peripheral devices takes place.
=DT/R : Data Transmit/Receive. This pin is required in minimum systems, that
want to use an 8286 or 8287 data bus transceiver. The direction of data flow is
controlled through the transceiver.

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• DEN: Data enable. This pin is provided as an output enable for
the 8286/8287 in a minimum system which uses transceiver.
DEN is active low(0) during each memory and input-output
access and for INTA cycles.
• HOLD/HOLDA: HOLD indicates that another master has been
requesting a local bus .This is an active high(1). The
microprocessor receiving the HOLD request will issue HLDA
(high) as an acknowledgement in the middle of a T4 or T1
clock cycle.
• ALE : Address Latch Enable. ALE is provided by the
microprocessor to latch the address into the 8282 or 8283
address latch. It is an active high(1) pulse during T1 of any bus
cycle. ALE signal is never floated, is always integer.
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System bus Structure

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 SYSTEM BUS TIMING

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Minimum Mode 8086 System
Read write cycle

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Read cycle timing diagram for minimum
mode

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Write cycle timing diagram for
minimum mode

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 Read cycle timing diagram for
maximum mode

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Write cycle timing diagram for
maximum mode

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Interrupt and Interrupt service
routine
• Interrupt is the method of creating a temporary halt
during program execution and allows peripheral devices
to access the microprocessor. The microprocessor
responds to that interrupt with an ISR (Interrupt Service
Routine), which is a short program to instruct the
microprocessor on how to handle the interrupt

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Hardware Interrupts
• Hardware interrupt is caused by any peripheral device by sending a signal through a
specified pin to the microprocessor.
• The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable
interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin
associated is INTA called interrupt acknowledge.
• NMI
• It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable
interrupt request pin (INTR)and it is of type 2 interrupt.
• When this interrupt is activated, these actions take place −
• Completes the current instruction that is in progress.
• Pushes the Flag register values on to the stack.
• Pushes the CS (code segment) value and IP (instruction pointer) value of the return address
on to the stack.
• IP is loaded from the contents of the word location 00008H.
• CS is loaded from the contents of the next word location 0000AH.
• Interrupt flag and trap flag are reset to 0.
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 INTR
• The INTR is a maskable interrupt because the microprocessor will be interrupted only if
interrupts are enabled using set interrupt flag instruction. It should not be enabled using
clear interrupt Flag instruction.
• The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled,
then the microprocessor first completes the current execution and sends ‘0’ on INTA pin
twice. The first ‘0’ means INTA informs the external device to get ready and during the
second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable interrupt
controller.
• These actions are taken by the microprocessor −
• First completes the current instruction.
• Activates INTA output and receives the interrupt type, say X.
• Flag register value, CS value of the return address and IP value of the return address are
pushed on to the stack.
• IP value is loaded from the contents of word location X × 4
• CS is loaded from the contents of the next word location.
• Interrupt flag and trap flag is reset to 0
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Types of interrupt
• TYPE 0 interrupt represents division by zero situation.
• TYPE 1 interrupt represents single-step execution
during the debugging of a program.
• TYPE 2 interrupt represents non-maskable NMI
interrupt.
• TYPE 3 interrupt represents break-point interrupt.
• TYPE 4 interrupt represents overflow interrupt.

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