UNIT-1

INTRODUCTION TO MICROCONTROLLERS
https://dokumen.tips/documents/mc-8051-mazidi.ht
ml?page=39
https://www.techulator.com/resources/11036-Micro
controller-block-diagram-components.aspx
http://download.mikroe.com/documents/
compilers/mikroc/8051/help/
8051_memory_organization.htm
 8051
Microcontroller

8051

2
 CONTENTS
• Overview of 8051 Microcontroller
• 8051 Architecture
• Pin Diagram
• Memory Organization
• Addressing Modes
• Instruction set of 8051
 Introduction to a Microcontroller
• A microcontroller is a highly integrated single chip, which consists
of on chip CPU (Central Processing Unit), RAM (Random Access
Memory), EPROM/PROM/ROM (Erasable Programmable Read
Only Memory), I/O (input/output) – serial and parallel, timers,
interrupt controller. For example, Intel 8051 is 8-bit microcontroller
and Intel 8096 is 16-bit microcontroller. The block diagram of
Microcontroller is shown below:
Overview of 8051 Microcontroller
Overview of 8051 Microcontroller

BLOCK DIAGRAM OF 8051

 Features of 8051

• The 8051 is an 8-bit microcontroller with 8 bit data bus and

16-bit address bus.
• The 16 bit address bus can address a 64K( 216) byte program
memory space and a separate 64K byte of data memory
space.
• The 8051 has 4K on-chip program memory (ROM) and 128
bytes of Data RAM
• On-chip clock oscillator
• 32 bidirectional I/0 lines (Port 0,1,2,3)
Port 0 { P0.0-P0.7 } – 8 pins
Port 1 { P1.0-P1.7 } – 8 pins
Port 2 { P2.0-P2.7 } – 8 pins
Port 3 { P3.0-P3.7 } – 8 pins
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• Two 16-bit timer/counters(Timer 1,Timer 0)
• One serial port
UART(Universal Asynchronous Receiver Transmitter)
• 6-source interrupt structure
1.External interrupt INT0
2.Timer interrupt T0
3.External interrupt INT1
4.Timer interrupt T1
5.Serial communication interrupt
6.Timer Interrupt T2
•4 Register Banks (Bank 0, Bank 1, Bank 2, Bank3) each
bank has R0-R7 registers
 General Block Diagram of 8051
External Interrupts

Interrupt 4K 128 Timer 0

Control ROM B Timer 1
RAM Count
er
Inputs
8bi
t
CP
UOSC Bus
4 I/O Ports
Serial
Control Port

TXD
P0 P1 P2 RXD
Pin diagram of 8051
 Pin Description Summary
PIN TYPE NAME AND FUNCTION

Vss (GND) I Ground: 0 V reference.

Vcc I Power Supply + 5V.

I/O Port 0: Port 0 is also the multiplexed low-order address and

data bus during accesses to external program and data
P0.0 - memory.
P0.7
I/O Port 1: Port 1 is an 8-bit bi-directional simple I/O port.
P1.0 -
P1.7
I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the
high order address byte
P2.0 -
P2.7

I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also

P3.0 - serves special features as explained.
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P3.7 1
 Pin Description Summary
PIN TYPE NAME AND FUNCTION
RST I Reset: resets the device.
ALE O Address Latch Enable:When ALE=0, it provides data D0-D7
When ALE=1, it has address A0-A7

PSEN* O Program Store Enable: acts as read strobe to external

program memory
For External Code Memory, PSEN = 0
For External Data Memory, PSEN = 1
EA*/VPP I External Access Enable/Programming Supply Voltage:
EA = 0, 8051 microcontroller fetches from
external program memory (ROM) only.
EA = 1, then it fetches from internal and
external program memories (ROMS).

XTAL1 and 1 Oscillator pins for generating an internal clock. External

XTAL2 oscillator is connected to these pins.
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 8051 Microcontroller Pin Description

Pins from 1-8

Pin 1 to Pin 8 are assigned to Port 1 for simple I/O operations.
They can be configured as input or output pins depending on
the logic control i.e.
 if logic zero (0) is applied to the I/O port it will act as an
output pin and
 if logic one (1) is applied the pin will act as an input pin.
These pins are also referred to as P1.0 to P1.7 (where P1
indicates that it is a pin in port 1 and the number after ‘.’ tells
the pin number i.e. 0 indicates first pin of the port. So, P1.0
means first pin of port 1, P1.1 means second pin of the port 1
and so on). These pins are bidirectional pins.
 8051 Microcontroller Pin Description
Pin 9
Reset pin. It is an active-high, input pin. Therefore if the RST pin is
high for a minimum of 2 machine cycles, the microcontroller will
reset i.e. it will close and terminate all activities. It is often referred
as “power-on-reset” pin because it is used to reset the
microcontroller to it’s initial values when power is on (high)

Pins from 10-17

Pin 10 to pin 17 are port 3 pins which are also referred to as P3.0 to
P3.7. These pins are similar to port 1 and can be used as universal
input or output pins. These pins are bidirectional pins.
 Port 3
• Port 3 can be used as input or output.

• Port 3 has the additional function of

providing some extremely important
signals

15
 8051 Microcontroller Pin Description
P3.0 (RXD) : 10th pin is RXD (serial data receive pin) which is for
serial input. Through this input signal microcontroller receives
data for serial communication.
P3.1 (TXD) : 11th pin is TXD (serial data transmit pin) which is
serial output pin. Through this output signal microcontroller
transmits data for serial communication.
P3.2 and P3.3 (INT0′, INT1′ ) : 12th and 13th pins are for
External Hardware Interrupt 0 and Interrupt 1 respectively.
When this interrupt is activated(i.e. when it is low), 8051 gets
interrupted in whatever it is doing and jumps to the vector
value of the interrupt (0003H for INT0 and 0013H for INT1) and
starts performing Interrupt Service Routine (ISR) from that
vector location.
 8051 Microcontroller Pin Description
P3.4 and P3.5 (T0 and T1) : 14th and 15th pin are for Timer 0 and
Timer 1 external input. They can be connected with 16 bit
timer/counter.
P3.6 (WR’) : 16th pin is for external memory write i.e. writing data
to the external memory.
P3.7 (RD’) : 17th pin is for external memory read i.e. reading data
from external memory.
 8051 Microcontroller Pin Description
Pin 18 and Pin 19 (XTAL2 And XTAL1) – These pins are
connected to an external oscillator which is generally a
quartz crystal oscillator. They are used to provide an external
clock frequency of 4MHz to 30MHz.

Pin 20 (GND) –This pin is connected to the ground. It has to

be provided with 0V power supply. Hence it is connected to
the negative terminal of the power supply.
Pins from 21-28
Pin 21 to pin 28 are port 2 pins also referred to as P2.0 to
P2.7. When additional external memory is interfaced with the
8051 microcontroller, pins of port 2 act as higher-order
address bytes. These pins are bidirectional.
 8051 Microcontroller Pin Description
Pin 29:Also called PSEN (Program Store Enable) it controls and
manages the access to external CODE memory. It is output, active-
low pin. This is used to read external memory.

Pin 30:Named as Address Latch Enable (ALE). It is an active-high

input control signal.It is used during external memory interfacing. ALE
pin is used for demultiplexting the address and data. It indicates to
the external latch that valid address information is present on the
bus.
During programming of the 8051 microcontroller, the PROG pin is
used to enter programming mode. By applying specific voltage levels
or sequences to this pin, the microcontroller can be programmed
Pin 31:Named as External Access (EA). It is used to enable/disable
external memory interfacing. In order to execute code from internal
memory this pin is connected to Vcc. To execute code from external
memory the pin must be grounded.
 8051 Microcontroller Pin Description

Pins from 32-39: Pin 32 to pin 39 are port 0 pins also referred
to as P0.0 to P0.7. They are bidirectional input/output pin. Port
0 is also designated as AD0-AD7 because 8051 multiplexes
address and data through port 0 to save pins.

Pin 40
Named as Vcc. This pin provides power supply voltage i.e. +5
Volts to the circuit.
 8051 Microcontroller Pin Description

I/O Pins
The 8051 microcontrollers are mostly 8-bit ports, thus giving a
total of 32 pins which you can use to read input and control
output. All of them are bidirectional in nature so they can perform
as both input and output.
 Some of the ports perform alternate functions as discussed
above such as to support access to external memory. This is done
to reduce the size of the microcontroller device. When these
ports are busy in performing their alternate functions, they can
not be made to act as input-output ports.
ARCHITECTURE OF 8051 MICROCONTROLLER
• The architecture of the 8051 microcontroller can be understood
from the block diagram. It has Harvard architecture with RISC
(Reduced Instruction Set Computer) concept.
• 8051 Microcontroller consists of
an 8-bit ALU
Oscillator
Interrupt Control
Bus Control
one 8-bit PSW(Program Status Word Register),
A and B registers ,
one 16-bit Program counter ,
one 16-bit Data pointer register(DPTR),
128 bytes of RAM and 4kB of ROM and
four parallel I/O ports each of 8-bit width
Intel 8051 Micro Architecture
 A and B CPU registers
• Totally 34 general purpose registers or working registers.
• Two of these A and B hold results of many instructions,
particularly math and logical operations of 8051.
• The other 32 are in four banks,B0 – B3 of eight registers each.
• The A register is also called the Accumulator and as it’s name
suggests, it is used to accumulate the results of a large number of
instructions. By default it is used for all mathematical operations
and also data transfer operations between CPU and any external
memory.
• The B register is mainly used for multiplication and division
operations along with A register. MUL AB : DIV AB.
• Register B holds high order byte of the result in the multiplication
and remainder in the division operation.
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Program Counter
• 16 bit register to hold the address of a byte in memory
• PC contains the address of the next instruction to be executed.
• After execution of one instruction the program counter is
incremented to point to the address of the next instruction to be
executed. Since the PC is 16-bit width ,8051 can access program
addresses from 0000H to FFFFH ,a total of 64KB of code.
Data Pointer
• DPTR is made up of two 8 bit register DPH and DPL;
• DPTR points to data. When the 8051 accesses external memory it
will access data at the address indicated by DPTR.
• DPTR contains the address of internal & external code and data that
has to be accessed.
• DPTR Register is usually used for storing address of
data and intermediate results.
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 Stack Pointer
• It is an 8-bit register which stores the address of the stack top.
• Stack Pointer is used to indicate where the next value to be
removed from the stack should be taken from. When 8051
microcontroller is powered up it contains 07H value. When a
value is pushed onto the stack, the 8051 first increments the value
of SP and then stores the value at the resulting memory location.
Similarly when a value is popped off the stack, the 8051 returns
the value from the memory location indicated by SP, and then
decrements the value of SP.
• STACK in 8051 Microcontroller: The stack is a part of RAM used by
the CPU to store information temporarily. This information may be
either data or an address .The CPU needs this storage area as there
are only limited number of registers. The register used to access
the stack is called the Stack pointer which is an 8-bit register. So ,it
can take values of 00 to FF H. 26
 Program Status Word Register (PSW)/ Flag Register

--
CY AC F0 RS1 RS0 OV P
Carry flag PSW.7 CY
Auxiliary carry flag PSW.6 AC
Available to the user for general purpose PSW.5 --
Register Bank selector bit 1 PSW.4 RS1
Register Bank selector bit 0 PSW.3 RS0
Overflow flag PSW.2 OV
User define bit PSW.1 --
Parity flag Set/Reset odd/even parity PSW.0 P

RS1 RS0 Register Bank Address

0 0 0 00H-07H

0 1 1 08H-0FH

1 0 2 10H-17H

1 1 3 18H-1FH

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P, the parity flag
The parity flag reflects the number of 1 s in the A (accumulator) register only.
 If the A register contains an odd number of Is, then P = 1. Therefore, P = 0 if A has an
even number of 1s.
OV, the overflow flag
 This flag is set whenever the result of a signed number operation is too large, causing
the high-order bit to overflow into the sign bit.
 In general, the carry flag is used to detect errors in unsigned arithmetic operations.
 The overflow flag is only used to detect errors in signed arithmetic operations.
Carry Flag
 This flag is set whenever there is a carry out from the D7 bit.
 This flag bit is affected after an 8-bit addition or subtraction.
 It can also be set to 1 or 0 directly by an instruction such as “SETB C” and “CLR
C” where “SETB C” stands for “set bit carry” and “CLR C” for “clear carry”.

AC, the auxiliary carry flag

 This flag is set if a carry is generated after 4 bits(Nibble).

 Special Function Registers(SFR)
Name Function Name Function

A Accumulator SBUF Serial Port data buffer

B Arithmetic SP Stack Pointer
DPH Addressing Ext Memory TMOD Timer/Counter mode
control
DPL Addressing Ext Memory TCON Timer/Counter control
IE Interrupt enable TL0 Timer0 lower byte
IP Interrupt Priority TH0 Timer0 higher byte
P0 I/O Port Latch TL1 Timer1 lower byte
P1 I/O Port Latch TH1 Timer1 higher byte
P2 I/O Port Latch
P3 I/O Port Latch
PCON Power Control
PSW Program Status Word
SCON Serial Port Control

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Clock:
Synchronization among internal operations can be achieved with
the help of clock circuits which are responsible for generating clock
pulses. During each clock pulse a particular operation will be carried
out, thereby, assuring synchronization among operations.
There are two pins XTAL1 and XTAL2 which form an oscillator circuit .
Internal RAM and ROM
ROM
• A code of 4K memory is incorporated as on-chip ROM in 8051. The 8051
ROM is a non-volatile memory meaning that its contents cannot be
altered and hence has a similar range of data and program memory, i.e,
they can address program memory as well as a 64K separate block of
data memory.

RAM
• The 8051 microcontroller is composed of 128 bytes of internal RAM. This
is a volatile memory since its contents will be lost if power is switched off.
These 128 bytes of internal RAM contains 32 working registers which in
turn constitutes 4 register banks (Bank 0-Bank 3) with each bank
consisting of 8 registers (R0 - R7). There are 128 addressable bits in the
internal RAM.
INTERNAL RAM
 ARCHITECTURE & BLOCK DIAGRAM OF 8051
MICROCONTROLLER
Four General Purpose Parallel Input/Output Ports:
• The 8051 microcontroller has four 8-bit input/output ports. These are:
PORT P0: When there is no external memory present, this port acts as a
general purpose input/output port. In the presence of external memory, it
functions as a multiplexed address and data bus. It performs a dual role.
PORT P1: This port is used for various interfacing activities. This 8-bit port is
a normal I/O port i.e. it does not perform dual functions.

PORT P2: Similar to PORT P0, this port can be used as a general purpose
port when there is no external memory but when external memory is
present it works in conjunction with PORT PO as an address bus. This is an 8-
bit port and performs dual functions.

PORT P3: PORT P3 behaves as a dedicated I/O port

 ARCHITECTURE & BLOCK DIAGRAM OF 8051
MICROCONTROLLER
• Interrupt Control
In 8051, 5 sources of interrupts are provided. They are:
a)2 external interrupt sources connected through INT0 and INT1
b) 3 internal interrupt sources- serial port interrupt(TI/RI), Timer Flag 0
and Timer Flag 1.

• Serial Data Communication

In 8051, the SBUF (Serial Port Data Buffer) register holds the data;
the SCON (Serial Control) register manages the data communication
and the PCON (Power Control) register manages the data transfer
rates. Further, two pins - RXD and TXD, establish the serial network.

The SBUF register has 2 parts – one for storing the data to be
transmitted and another for receiving data from outer sources. The
first function is done using TXD pin and the second function is done
 8051 Memory Organization
• The 8051 microcontroller has 128 bytes of Internal RAM and 4kB
of on chip ROM .
• The RAM is also known as Data memory and the ROM is known as
program memory. The program memory is also known as Code
memory .This Code memory holds the actual 8051 program that is
to be executed.
• In 8051 this memory is limited to 64K .Code memory may be
found on-chip, as ROM or EPROM .
• It may also be stored completely off-chip in an external ROM or,
more commonly, an external EPROM.
• The 8051 has only 128 bytes of Internal RAM but it supports 64kB
of external RAM. Since the memory is off-chip it is not as flexible in
terms of accessing, and is also slower.
 8051 Memory Organization

60K

64K
64K

4K

36
8051 Memory Organization
• The upper addresses and SFRs occupy the same block of
address space, 80H through FFH, although they are
physically separate entities.
• The upper address space is accessible by indirect
addressing only and SFRs are accessible by direct
addressing only.
• The lower address space can be accessed either by direct
addressing or by indirect addressing
• The 8051 can address up to 64 Kbytes of external data
memory.
• The “MOVX” instruction is used to access the external
data memory.
8051 Memory Organization
• Internal RAM OF 8051: The 128 bytes of
internal RAM is organized as below.
(i) Four register banks (Bank0, Bank1, Bank2
and Bank3) each of 8-bytes (total 32 bytes).
The default bank register is Bank0. The
remaining Banks are selected with the help
of RS0 and RS1 bits of PSW Register.
(ii) 16 bytes of bit addressable area and
(iii) 80 bytes of general purpose area (Scratch
pad memory). This area is also utilized by the
microcontroller as a storage area for the
operating stack.
•The 32 bytes of RAM from address 00 H to 1FH
are used as working registers organized as four
banks of eight registers each. The registers are
named as R0-R7 .Each register can be addressed
by its name or by its RAM address.
 Data memory organization in 8051:Upper 128 Bytes of RAM

• The upper 128B of the RAM i.e. memory addresses from 80H to
FFH is allocated for Special Function Registers (SFRs). SFRs
control specific functions of the 8051 Microcontroller. Some of
the SFRs are I/O Port Registers (P0, P1, P2 and P3), PSW
(Program Status Word), A (Accumulator), IE (Interrupt Enable),
PCON (Power Control), etc.
• SFRs Memory addresses are only direct addressable. Even
though some of the addresses between 80H and FFH are not
assigned to any SFR, they cannot be used as additional RAM
area.
• In some microcontrollers, there is an additional 128B of RAM,
which share the memory address with SFRs i.e. 80H to FFH.
But, this additional RAM block is only accessed by indirect
addressing.
 Special Function Registers (SFRs)

• SFRs provide control

and data exchange
with the
microcontroller’s
resources and
peripherals
• Registers which have
their byte addresses
ending with 0H or 8H
are byte- as well as bit-
addressable
• Some registers are not
bit-addressable. These
include the stack
pointer (SP) and data
pointer register (DPTR)
8051 Memory Organization
• Program Memory (ROM) organization of 8051: In
8051 Microcontroller, the code or instructions to
be executed are stored in the Program Memory,
which is also called as the ROM of the
Microcontroller
• The 8051 microcontroller has 4kB of on chip ROM but it can be
extended up to 64kB.This ROM is also called program memory or code
memory. The external ROM is accessed when the EA(active low) pin is
connected to ground .
• When the EA Pin is high, the CPU first fetches instructions from the
Internal Program Memory in the address range of 0000H to 0FFFH and
if the memory addresses exceed the limit, then the instructions are
fetched from the external ROM in the address range of 1000H to FFFFH.
When the Internal ROM address is exceeded the 8051 automatically
fetches the code bytes from the external program memory.
• Another way to fetch the instructions is to ignore the Internal
ROM and fetch all the instructions only from the External Program
Memory (External ROM).
• For this scenario, the EA Pin must be connected to GND. In this
case, the memory addresses of the external ROM will be from
0000H to FFFFH.
 Addressing Modes
• The way in which the data operands are accessed by
different instructions is known as the addressing
modes. There are various methods of denoting the data
operands in the instruction.
The 8051 microcontroller supports mainly 5 addressing
modes. They are
1.Immediate addressing mode
2.Direct Addressing mode
3.Register addressing mode
4.Register Indirect addressing mode
5.Indexed addressing mode
 Immediate Addressing Mode
• The addressing mode in which the data operand is a constant and
it is a part of the instruction itself is known as Immediate
addressing mode.
• Normally the data must be preceeded by a # sign. This addressing
mode can be used to transfer the data into any of the registers
including DPTR.
• The immediate data sign, “#”
Examples:
• MOV A , # 27 H ;The data (constant) 27H is moved to the
accumulator register
• ADD R1 ,#45 H ; Add the constant 45 to the contents of the
accumulator
• MOV DPTR ,# 8245H :Move the data 8245 into the data pointer
register.
• MOV P1,#21 H ;The data (constant) 21H is moved to the port P1
45
 Register Addressing Mode
• The addressing mode in which the data operand to be
manipulated lies in one of the registers is known as register
addressing mode.

Examples:
• MOV A,R0 : Move the contents of the register R0 to the
accumulator
• ADD A,R6 :Add the contents of R6 register to the accumulator
• MOV P1, R2 : Move the contents of the R2 register into port 1
• MOV R5, R2 : This is invalid .The data transfer between the
registers is not allowed.

46
 Direct Addressing Mode
• The addressing mode in which the data operand is in the RAM
location (00 -7FH) and the address of the data operand is
given in the instruction is known as Direct addressing mode.
• The direct addressing mode uses the lower 128 bytes of
Internal RAM and the SFRs .
• This mode allows you to specify the operand by giving its
actual memory address

Examples:
MOV R1, 42H : Move the contents of RAM location 42 into R1
register
MOV 49H,A : Move the contents of the accumulator into the
RAM location 49.
ADD A, 56H : Add the contents of the RAM location 56 to the
accumulator 47
 Register Indirect Addressing Mode
• The addressing mode in which a register is used as a pointer to the
data memory block is known as Register indirect addressing mode.
• In this mode, register is used as a pointer to the data.
• The operands are specified using the 8-bit address
• The address register for 16-bit addresses can only be Data pointer
(DPTR)
• Only register R0 and R1 are used for this purpose.
• R2-R7 cannot be used to hold the address of an operand located in
RAM.
• When R0 and R1 hold the addresses of RAM locations, they must be
preceded by the “@” sign.

Examples:
• MOV A,@ R0 :Move the contents of RAM location whose address is in
R0 into A
• MOV @ R1 , B : Move the contents of B into RAM location whose
address is held by R1
48
• MOVX A, DPTR Moves contents of DPTR to A
 Indexed Addressing Mode for ROM Access
• This mode is widely used in accessing data elements of look-up table
entries located in the program (code) space ROM at the 8051
• The address of the operand is formed by adding the contents
of A and DPTR.
MOVC A,@A+DPTR
A= content of address A +DPTR from ROM
.In this instruction the contents of A are added to the 16-bit DPTR
register to form the 16-bit address of the data operand.
Note:
Because the data elements are stored in the program (code ) space ROM
of the 8051, it uses the instruction MOVC instead of MOV. The “C”
means code.

49
 8051 Instruction Set
•An "instruction" refers to a command or operation that the
microcontroller executes.
The format of instruction is as follows:
MNEMONIC OPERANDS
•The first part of each instruction, called MNEMONIC refers to the
operation an instruction performs Mnemonics are abbreviations of
the name of operation being executed.
•The other part of instruction, called OPERAND is separated from
mnemonic by at least one whitespace and defines data being
processed by instructions.
If there is more than one operand in an instruction, they are separated
by a comma.
Eg: INC R1 - Increment register R1 (increment register R1);
RET - return from a subroutine; no operand
JZ TEMP - if the number in the accumulator is 0, jump to the
address marked as TEMP;
ADD A,R3 - add R3 and accumulator;
 8051 Instruction Set
The following nomenclatures for register, data, address and
variables are used while write instructions.
• A: Accumulator
• B: "B" register
• C: Carry bit
• Rn: Register R0 - R7 of the currently selected register bank
• Direct: 8-bit internal direct address for data. The data could be in
lower 128bytes of RAM (00 - 7FH) or it could be in the special
function register (80 - FFH).
• @Ri: 8-bit external or internal RAM address available in register
R0 or R1. This is used for indirect addressing mode.
• #data8: Immediate 8-bit data available in the instruction.
• #data16: Immediate 16-bit data available in the instruction.
• bit: Directly addressed bit in internal RAM or SFR
51
 Instruction Groups

• The 8051 instructions are grouped into 5 groups

– Arithmetic Instructions
– Logic Instructions
– Data Transfer Instructions
– Boolean Instructions
– Program Branching Instructions
 Arithmetic Instructions
• Arithmetic instructions perform several basic operations such
as addition, subtraction, division, multiplication etc.
• After execution, the result is stored in the first operand.
• These instructions implement arithmetic and logical
operations along with increment, decrement and decimal
adjust operations.
• There are no SUB or Compare instructions.
• Also, the operations performed by the arithmetic instructions
affect flags like carry, overflow, zero, etc. in the PSW Register.
 Arithmetic Instructions
Mnemonic Description
ADD Addition without Carry
ADDC Addition with Carry
SUBB Subtract with Borrow
INC Increment by 1
DEC Decrement by 1
MUL Multiply
DIV Divide
DAA Decimal Adjust the Accumulator (A
Register)

54
• ADD
– 8-bit addition between the accumulator (A) and a second
operand.
• The result is always in the accumulator.
• The CY flag is set/reset appropriately.
• Eg: ADD A, R1
• ADDC
– 8-bit addition between the accumulator, a second operand and
the previous value of the CY flag.
• Useful for 16-bit addition in two steps.
• The CY flag is set/reset appropriately.
• Eg: ADDC A, R1

55
• DAA
– Decimal adjust the accumulator.
• Format the accumulator into a proper 2 digit packed BCD
number.
• Operates only on the accumulator.
• Works only after the ADD instruction.
• SUBB
– Subtract with Borrow.
• Subtract an operand and the previous value of the borrow
(carry) flag from the accumulator.
– A  A - <operand> - CY.
– The result is always saved in the accumulator.
– The CY flag is set/reset appropriately.
Eg: SUBB A, R1
• MUL AB
– Multiply A by B and place result in A & B.
– lower byte of result stored in A, higher byte in B

•DIV AB
– Divide A by B and place result quotient in A and remainder in B.

• INC
– Increment the operand by one.
• The operand can be a register, a direct address, an indirect
address, the data pointer.
• Eg: INC A
• DEC
– Decrement the operand by one.
• The operand can be a register, a direct address, an indirect
address.
• Eg: DEC A
Arithmetic Instructions
Arithmetic Instructions

59
 Data Transfer Instructions
• Data transfer instructions move the content of one register to
another.
• These instructions are associated with transfer of data between
registers or external program memory or external data memory.
• The register the content of which is moved remains unchanged.
Mnemonic Description
MOV Move Data
MOVC Move Code
MOVX Move External Data
PUSH Move Data to Stack
POP Copy Data from Stack
XCH Exchange Data between two Registers
 Data Transfer Instructions

• MOV
– 8-bit data transfer for internal RAM and the SFR.
• Eg: MOV A, Rn
• MOV
– 1-bit data transfer involving the CY flag
• Eg: MOV C, bit
MOV bit, C
• MOV
– 16-bit data transfer involving the DPTR
• Eg: MOV DPTR, #data
• MOVC
– Move Code Byte
• Load the accumulator with a code byte from external
program memory.
• Must use indexed addressing
• Eg: MOVC A, @A+DPTR
MOVC A, @A+PC
• MOVX
– Data transfer between the accumulator and a byte from external
data memory.
• Eg: MOVX A, @Ri
MOVX A, @DPTR
MOVX @Ri, A
MOVX @DPTR, A
• PUSH / POP
– Push and Pop a data byte onto the stack.
– The data byte is identified by a direct address from the internal
RAM locations.
– Eg: PUSH DPL
POP 40H
• XCH
– Exchange accumulator and a byte variable
• XCH A, Rn
• XCHD
– Exchange lower digit of accumulator with the lower digit of the
memory location specified.
• XCHD A, @Ri
• The lower 4-bits of the accumulator are exchanged with the
lower 4-bits of the internal memory location identified
indirectly by the index register.
• The upper 4-bits of each are not modified.
 Logical Operations
• Logic instructions perform logic operations like AND, OR, XOR,
NOT, Rotate, Clear and Swap upon corresponding bits of two
registers. After execution, the result is stored in the first
operand. Mnemonic Description
ANL Logical AND
ORL Logical OR
XRL Ex-OR
CLR Clear Register
CPL Complement the Register
RL Rotate a Byte to Left
RLC Rotate a Byte and Carry Bit to Left
RR Rotate a Byte to Right
RRC Rotate a Byte and Carry Bit to Right
SWAP Exchange lower and higher nibbles in
a Byte
• ANL (Logical AND) / ORL (Logical OR)
– Work on byte sized operands or the CY flag.
• Eg: ANL A, Rn
ANL A, direct
ORL A, Rn
• XRL (Exclusive-OR)
– Works on bytes only.
– Eg: XRL A, Rn
• CPL / CLR
– Complement / Clear.
– Work on the accumulator or a bit.
Eg: CPL P1.2, CLR A
• RL / RLC / RR / RRC
– Rotate the accumulator.
• RL and RR without the carry
• RLC and RRC rotate through the carry.
• Eg: RL A, RRC A
• SWAP A
– Swap the upper and lower nibbles of the accumulator.
 Boolean Variable Instructions
• This group of instructions is associated with the single-bit
operations of the 8051.
• This group allows manipulating the individual bits of bit
addressable registers and memory locations as well as the CY
flag.
– TheMnemonic
P, OV, and AC flags Description
cannot be directly altered.
CLR Clear a Bit (Reset to 0)
SETB Set a Bit (Set to 1)
MOV Move a Bit

ANL Bitwise AND

ORL Bitwise OR
CPL Complement the Bit
• CLR
– Clear a bit or the CY flag.
• CLR P1.1
• CLR C
• CPL
– Complement a bit or the CY flag.
• CPL 40H ; Complement bit 40 of the bit
addressable memory
• SETB
– Set a bit or the CY flag.
• SETB A.2
• SETB C
• ORL / ANL
– OR / AND a bit with the CY flag.
• ORL C, 20H ; OR bit of bit address 20h in bit addressable
memory with the CY flag
• ANL C, /34H ; AND complement of bit of bit address 34h
in bit addressable memory with the CY flag.
• MOV
– Data transfer between a bit and the CY flag.
• MOV C, 3FH ; Copy the CY flag to bit of bit address 3Fh of
the bit addressable memory.
• MOV P1.2, C ; Copy the CY flag to bit 2 of P1.
5. Program Branching Instructions
Mnemonic Description
LJMP Long Jump (Unconditional)
AJMP Absolute Jump (Unconditional)
SJMP Short Jump (Unconditional)
JZ Jump if A is equal to 0
JNZ Jump if A is not equal to 0
CJNE Compare and Jump if Not Equal
DJNZ Decrement and Jump if Not Zero
NOP No Operation
LCALL Long Call to Subroutine
ACALL Absolute Call to Subroutine
(Unconditional)
RET Return from Subroutine
RETI Return from Interrupt
JMP Jump to an Address (Unconditional)
 Program Branching Instructions
• These instructions control the flow of program logic.
• Some of these instructions has decision making capability
before transferring control to other part of the program.
• There are two kinds of branch instructions:
 Unconditional jump instructions:
Upon their execution a jump to a new location
from where the program continues execution is
executed.
 Conditional jump instructions:
A jump to a new program location is executed
only if a specified condition is met. Otherwise, the
program normally proceeds with the next instruction.
• The 8051 provides four different types of unconditional jump
instructions:
– Short Jump – SJMP
• Uses an 8-bit signed offset relative to the 1st byte of the
next instruction.
• Eg: SJMP rel ; Short jump from -128 to +127 locations
– Long Jump – LJMP
• Uses a 16-bit address.
• 3 byte instruction capable of referencing any location in
the entire 64K of program memory.
• Eg: LJMP addr16 ; range : 0000H to FFFFH
– Absolute Jump – AJMP
• Uses an 11-bit address.
• The upper 3-bits of the address combine with the 5-bit
opcode to form the 1st byte and the lower 8-bits of the
address form the 2nd byte.
• The 11-bit address is substituted for the lower 11-bits of
the PC to calculate the 16-bit address of the target.
• Absolute jump is within 2K byte memory.
• Eg: AJMP addr11 ; range : 0000H to 07FFH
– Indirect Jump –
• Makes an indirect jump to the specified location.
• Eg: JMP @A + DPTR
• CALL instruction is used to call a subroutine.
• Subroutines are often used to perform tasks that need to be
performed frequently.
• It is a 3-byte instruction.
• The 8051 provides 2 forms for the CALL instruction:
– Absolute Call – ACALL
• Uses a 11-bit address similar to AJMP
• The subroutine must be within the same 2K block.
• Eg: ACALL addr11
– Long Call – LCALL
• Uses a 16-bit address similar to LJMP
• The subroutine can be anywhere within 64KB address
space
• Eg: LCALL addr16
– Both forms push the 16-bit address of the next instruction on
the stack and update the stack pointer. 79
• The 8051 provides 2 forms for the return instruction:
– Return from subroutine – RET
• Pops the return address from the stack, updates stack
pointer and continues execution at the previously pushed
address.
– Return from Interrupt – RETI
• Pops the return address from the stack.
• Restores the interrupt logic to accept additional interrupts at
the same priority level as the one just processed.
• The PSW is not automatically restored to its pre-interrupt
status.
• Continues execution at the address retrieved from the stack.
• The 8051 supports 5 different conditional jump instructions.
– ALL conditional jump instructions use an 8-bit signed
offset.
– Jump on Zero – JZ / JNZ
• JZ rel ; Jump if accumulator is zero.
• JNZ rel ; Jump if accumulator is not zero.
– The check is done at the time of the instruction
execution.
– Jump on Carry – JC / JNC
• JC rel ; Jump if the C flag is set.
• JNC rel ; Jump if no carry flag.
– Jump on Bit – JB / JNB
• JB bit,rel ; Jump if the specified bit is set
• JNB bit, rel ; Jump if specified bit not set.
• Any addressable bit can be specified.
 – Jump if the Bit is set then Clear the bit – JBC
• JBC bit, rel ; Jump if the specified bit is set.
• Then clear the bit.

• Compare and Jump if Not Equal – CJNE

– Compare the magnitude of the two operands and jump if
they are not equal.
• The values are considered to be unsigned.
• CJNE <dest-byte>, <src-byte>, rel
• The Carry flag is set if <dest-byte> is less than <src-
byte> otherwise cleared.
 CJNE A, direct, rel
 CJNE A, #data, rel
• Decrement and Jump if Not Zero – DJNZ
– Decrement the first operand by 1 and jump to the location
identified by the second operand if the resulting value is
not zero.
– DJNZ <byte>, <rel-addr>
 DJNZ Rn, rel
 DJNZ direct, rel

• No Operation
– NOP
 Simple Programs
1.Write an ALP to add two 8-bit numbers 20H and 30H ,store the
result in the internal RAM Location Address 10H and display same
result at Port0 (P0) .
ORG 0000H ; Originate at 0000H
MOV A,#20H ;copy immediate 8-bit data 20H into A (Accumulator)
register
ADD A,#30H ;add the immediate 8-bit data 30H to the contents of A
and store the result in A
MOV 10H,A ;Move the result from A into Internal RAM(IRAM) address
10H
MOV P0,A ; Display the result at port0 (P0)
END ; stop
 Simple Programs
2.Write an ALP to add two 8-bit numbers stored in the internal RAM
address at 30H and 40H and store the result in the internal RAM
Location Address 50H
Program:
ORG 0000H ; Originate at 0000H
MOV R0,#30H ; InitiAlize R0 with internal RAM address of the first 8-
bit number
MOV A,40H ; Copy the data from the address 40H in to A
ADD A,@R0 ; Add the contents of memory location, address(30H)
stored in R0 to A
MOV 50H,A ; store the result from A in to memory location address
50H
END
 Simple Programs

3.Write an ALP to add two 8-bit numbers stored in the internal RAM
address at 30H and 40H and store the result in the External RAM
Location Address 2050H

ORG 0000H ; Originate at 0000H

MOV R0,#30H ; Initialize R0 with internal RAM address of the first 8-
bit number
MOV A,40H ; Copy the data from the address 40H in to A
MOV DPTR,#2050H ; initilize DPTR with 2050H
ADD A,@R0 ; Add the contents of memory location, address stored
in R0 to A
MOVX @DPTR,A ; Store the result from A in to External memory
location address(2050H) stored in DPTR
END
 SPECIAL FUNCTION REGISTERS (SFRs)
• There are many ways to categorize these 21 Special Function
Registers but the following way as an appropriate one. The 21 Special
Function Registers of 8051 Microcontroller are categorized in to 6
groups. They are:
• Math or CPU Registers: A and B
• Status Register: PSW (Program Status Word)
• Pointer Registers: DPTR (Data Pointer – DPL, DPH) and SP (Stack
Pointer)
• I/O Port Latches: P0 (Port 0), P1 (Port 1), P2 (Port 2) and P3 (Port 3)
• Peripheral Control Registers: PCON, SCON, TCON, TMOD, IE and IP
• Peripheral Data Registers: TL0, TH0, TL1, TH1 and SBUF
 8051 Microcontroller Special Function
Registers (SFRs)

I/O Port Registers (P0, P1, P2 and P3)

The 8051 Microcontroller four Ports which can be used as
Input and/or Output. These four ports are P0, P1, P2 and P3.
Each Port has a corresponding register with same names (the
Port Registers are also P0, P1, P2 and P3). The addresses of the
Port Registers are as follows: P0 – 80H, P1 – 90H, P2 – A0H and
P2 – B0H.
 8051 Microcontroller Special Function Registers (SFRs)
Peripheral Control Registers
TCON (Timer Control)
Timer Control or TCON Register is used to start or stop the Timers of
8051 Microcontroller.
TF TR TF TR IE IT1 IE0 IT
1 1 0 0 1 0
Timer Timer0 for Interrupt
1
TMOD (Timer Mode)
The TMOD or Timer Mode register or SFR is used to set the Operating
Modes of the Timers T0 and T1. The lower four bits are used to
configure Timer0 and the higher four bits are used to configure
Timer1.
 8051 Microcontroller Special Function Registers (SFRs)
Peripheral Control Registers
PCON (Power Control)
The PCON or Power Control register, as the name suggests is used to
control the 8051 Microcontroller’s Power Modes.

SCON (Serial Control)

The Serial Control or SCON SFR is used to control the 8051
Microcontroller’s Serial Port.
 8051 Microcontroller Special Function Registers (SFRs)
IE (Interrupt Enable)
The IE or Interrupt Enable Register is used to enable or disable
individual interrupts.
IP (Interrupt Priority)
The IP or Interrupt Priority Register is used to set the priority of the
interrupt as High or Low.
Peripheral Data Registers
SBUF (Serial Data Buffer)
The Serial Buffer or SBUF register is used to hold the serial data while
transmission or reception.
TL0/TH0 (Timer 0 Low/High)
The Timer 0 consists of two SFRs: TL0 and TH0. The TL0 is the lower
byte and the TH0 is the higher byte and together they form a 16-bit
Timer0 Register.
TL1/TH1 (Timer 1 Low/High)
The TL1 and TH1 are the lower and higher bytes of the Timer 1.