Unit-2 Test Generation for Combinational Logic Circuits

Introduction :
CO-2 Analyze and design test patterns for combinational logic circuits (L2)

At the end of this topic, the students will be able to

TLO1: analyze and design test patterns using truth table method, fault matrix
method, Boolean difference method and path sensitization method
TLO2: design test patterns using D-Roth algorithm, PODEM algorithm and FAN
algorithm

ECE16 VLSI Testing and Verification VIII Semester

Contd.

Test Generation for Combinational Logic Circuits:

 Test Generation Techniques for Combinational Circuits: Truth table method,

 Fault matrix method,
 Boolean difference method,
 Path sensitization method,
 D-Roth algorithm, PODEM and FAN.
8 Hrs

ECE16 VLSI Testing and Verification VIII Semester

Introduction
 The aim of testing at the gate level is to verify that each logic gate in the circuit
is functioning properly and the interconnections are good
 If only a single stuck-at fault is assumed to be present in the circuit under test,
then the problem is to construct a test set that will detect the fault by utilizing
only the inputs and the outputs of the circuit.
 One of the main objectives in testing is to minimize the number of test patterns
 If the function of a circuit in the presence of a fault is different from its normal
function (nonredundant), then an n-input combinational circuit can be completely
tested by applying all 2n combinations to it
 2n increases very rapidly as n increases
 Fortunately Complete truth table exercise of the logic circuit is not necessary
only the input combinations that detect most of the faults in the circuit are
required.

ECE16 VLSI Testing and Verification VIII Semester

Cont.
 The efficiency of a test set is measured by a figure of merit called fault coverage
 Fault coverage refers to the percentage of the possible single stuck-at faults that
a test set will detect

ECE16 VLSI Testing and Verification VIII Semester

Test Generation for Combinational Logic Circuits

 Several distinct test generation methods have been developed over the years
for combinational circuits.
 These methods are based on the assumptions that a circuit is nonredundant and
only a single stuck-at fault is present at any time

Truth Table and Fault Matrix

 The most straightforward method for generating tests for a particular fault is to
compare the responses of the fault-free and the faulty circuit to all possible input
combinations
 Any input combination for which the output responses do not match is a test for
the given fault

ECE16 VLSI Testing and Verification VIII Semester

Cont.

 Let the inputs to a combinational

circuit be x1, x2 and x3 and let Z be the
output of the circuit
 Let Z be the output of the circuit in
the presence of the fault  s-a-0
 Z be the output of the circuit in the
presence of  s-a-1
 Then for each row of the truth table,
ZZ and ZZ is computed; if the
result is 1, the input combination
corresponding to the row is a test for
the fault

ECE16 VLSI Testing and Verification VIII Semester

Example


Circuit under test 

Fault Matrix 

ECE16 VLSI Testing and Verification VIII Semester

Cont.

 Fault Matrix

Minimal test set



ECE16 VLSI Testing and Verification VIII Semester

Cont.
F1 s-a-1 F4 s-a-1
A

B F2 s-a-0
f
F6 s-a-1

C
F3 s-a-0 F5 s-a-0

A B C F F1 F2 F3 F4 F5 F6 FF1 FF2 FF3 FF4 FF5 FF6

0 0 0 1 1 1 1 1 0 1 1

0 0 1 0 0 0 1 1 0 1 1 1 1

0 1 0 1 1 1 1 1 0 1 1

0 1 1 0 1 0 1 1 0 1 1 1 1 1

1 0 0 1 1 1 1 1 0 1 1

1 0 1 0 0 0 1 1 0 1 1 1 1

1 1 0 1 1 1 1 1 1 1

1 1 1 1 1 0 1 1 1 1 1

Truth Table Fault Matrix

ECE16 VLSI Testing and Verification VIII Semester
Cont.

A B C FF1 FF2 FF3 FF4 FF5 FF6

0 0 0 1
0 0 1 1 1 1
0 1 0 1
0 1 1 1 1 1 1
1 0 0 1
1 0 1 1 1 1
1 1 0
1 1 1 1

A B C FF1 FF2 FF3 FF4 FF5 FF6

0 0 0 1

0 1 1 1 1 1 1
1 1 1 1

Minimal Test set

ECE16 VLSI Testing and Verification VIII Semester

Cont.
 This fault matrix approach to test generation is not practicable when the
number of input variables is large

Path Sensitization
 The basic principle of the path sensitization method is to choose some path
from the origin of the fault to the circuit output
 A path is sensitized if the inputs to the gates along the path are assigned
values such that the effect of the fault can be propagated to the output

ECE16 VLSI Testing and Verification VIII Semester

Cont.

Example
0
A
1/0
1
B 0/1
G3
C
0 1 s-a-1
G1 G2
Input NAND NOR
 Forward Trace
 G2 = 0, Both inputs to G2 must be 1, A B Y Y

 A=0 0 0 1 1

 Backward Trace 0 1 1 0
 B = 1 and G1 = 1 1 0 1 0
 C=0 1 1 0 0
 Test Vector : ABC = 010

ECE16 VLSI Testing and Verification VIII Semester

Cont.
Example 1 1/0
4
0/1
2 s-a-1 6
3
1/0
1
5

 H = 0, G2 = 0 or E =0 or both G2 and E = 0 Input AND OR NOR

A B Y Y Y
 G1 = 0, G5 = 1
0 0 1 0 1
 To make G3 = 0, G2 = 0, C = D = 0, E = X or 0 1 1 1 0
 If E = 0, G2 = X, C = D = X 1 0 1 1 0

 G1 = 0, A = B = 0 or A = 0, B = X or A = X, B = 0 1 1 0 1 0

 G5 = 1, F = 0
 Test Vector, ABCDEF = 0000X0, 0XXX00, X0XX00 …………

ECE16 VLSI Testing and Verification VIII Semester

Example

Input NAND
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

 Assume that line  is s-a-1.

 To test for , both G3 and C must be set at 1
 In addition, D and G6 must be set at 1 so that G7=1
 To propagate the fault from G7 to the circuit output f via G8 requires the output
of G4 to be 1
 This is because if G4=0, the output f will be forced to be 1, independent of the
value of gate G7.
 For G3=1, A=0, C=1, For G6=1, B=0 (Since C=1), D=1
 Test Vector : ABCD = 0011
ECE16 VLSI Testing and Verification VIII Semester
Problem

Find the test pattern by using path sensitization method?

Input NAND
A
G1
B A B Y
0 0 1
G4 f 0 1 1
1 0 1
G2
G3 1 1 0

C S-a-0

Test Vector : ABC = 01X or 0X0

A test pattern generated by the path sensitization method may not be unique.

ECE16 VLSI Testing and Verification VIII Semester

Problem
Find the test pattern by using path sensitization method?

Input NOR

A B Y
0 0 1
s-a-0 0 1 0
1 0 0
1 1 0

 Path : G6, G8
 For  s-a-0, to sensitize the fault: G2=1, B=C=0,
 To propagate the fault through G6 and G8: D=0, G4=G5=G7=0
 Since B and D=0 is already set, G3=1, G7=0
 To set G5=0: A=1 hence G1=0, To make G4=0, B must be = 1, but B=0 already
set , not possible to set G4 o/p to 0 Hence not possible to propagate
ECE16 VLSI Testing and Verification VIII Semester
Problem
Find the test pattern by using path sensitization method?

Input NOR

A B Y
0 0 1
s-a-0 0 1 0
1 0 0
1 1 0

 Path : G5, G8
  s-a-0, to sensitize the fault: G2=1, B=C=0,
 To propagate the fault through G5 and G8: A=0, G4=G6=G7=0
 For G6=0, D=1, Since B=0 and D=1, G3=0,
 To set G7=0, C must be=1, but already C is set 0 to sensitize fault
 A=0, D=1, G1=0, To set G4=0, B must be=1, Hence not possible to propagate
ECE16 VLSI Testing and Verification VIII Semester
Problem
Find the test pattern by using path sensitization method?

Input NOR

A B Y
0 0 1
s-a-0 0 1 0
1 0 0
1 1 0

 Assume ABCD=0000
 G2=1/0, G1=1, G3=1, G4=0, G5=0/1, G6=0/1, G7=0
 G8=1/0

This example shows the necessity of sensitizing more than one path in deriving
tests for certain faults

ECE16 VLSI Testing and Verification VIII Semester

• The main drawback of the path sensitization
method is that only one path is sensitized at a
time. This does not guarantee that a test will
be found for a fault even if one exists.
• It’s necessary to sensitize more than one path
in deriving tests for certain faults and is the
principal idea behind the D-algorithm.

19
D - Algorithm

 The D-algorithm is guaranteed to find a test if one exists for detecting a fault
1. Generate / Trigger fault
2. Propagate fault from its origin to output
3. Consistency set of inputs for detecting the fault
 It uses a cubical algebra for automatic generation of tests
 Three types of cubes are considered
 Singular Cube
 Propagation D Cube
 Primitive D cube of a fault

ECE16 VLSI Testing and Verification VIII Semester

Cont.

 Singular Cube: nothing but a compact version of a truth table

 A Singular cube corresponds to a prime implicant of a function
 X’s or blanks are used to denote that the position may be either 0 or 1
 AND gate A B Y A B Y
0 0 0 0 X 0
0 1 0 X 0 0
1 0 0 1 1 1
1 1 1

 OR gate A B Y A B Y
0 0 0 0 0 0
0 1 1 1 X 1
1 0 1 X 1 1
1 1 1

ECE16 VLSI Testing and Verification VIII Semester

Cont.

 NAND gate A B Y A B Y
0 0 1 0 X 1
X 0 1
0 1 1
1 1 0
1 0 1
1 1 0

 NOR gate A B Y A B Y
0 0 1 0 0 1
0 1 0 1 X 0
X 1 0
1 0 0
1 1 0

 NOT gate A Y
0 1
1 0

A Y
 Buffer
0 0
1 1

ECE16 VLSI Testing and Verification VIII Semester

D - Intersection

ECE16 VLSI Testing and Verification VIII Semester

Primitive D Cube of faults (PDCf)

 The PDCf is used to specify the existence of a given fault

 It consists of an input pattern which shows the effect of a fault on the output of
the gate
AND gate
A s-a-0

B Y

A B Y A B Y
0 X 0 X X 0
X 0 0
1 1 1

A B Y
1 1 D

ECE16 VLSI Testing and Verification VIII Semester

Cont.

AND gate

A s-a-1

B Y

A B Y A B Y
0 X 0 X X 1
X 0 0
1 1 1

A B Y
0 X D
X 0 D

ECE16 VLSI Testing and Verification VIII Semester

Cont.

OR gate
A s-a-0

B Y

A B Y A B Y A B Y
0 0 0 X X 0 1 X D
1 X 1 X 1 D
X 1 1

A s-a-1 A B Y A B Y
0 0 0 X X 1
Y 1 X 1
B
X 1 1
A B Y
0 0 D

ECE16 VLSI Testing and Verification VIII Semester

Cont.

NAND gate A B Y A B Y
0 X 1 X X 0
A s-a-0 X 0 1
A B Y
1 1 0
B Y 0 X D
X 0 D

A s-a-1
A B Y A B Y
Y 0 X 1 X X 1
B
X 0 1
A B Y
1 1 0
1 1 D

ECE16 VLSI Testing and Verification VIII Semester

Cont.

NOR gate A B Y A B Y
0 0 1 X X 0
A s-a-0 1 X 0
A B Y
X 1 0
B Y 0 0 D

A B Y A B Y
0 0 1 X X 1
A s-a-1 1 X 0
A B Y
X 1 0
B Y 1 X D
X 1 D

ECE16 VLSI Testing and Verification VIII Semester

Cont.

NOT gate A Y
A Y A Y
A s-a-0 0 1
X 0 0 D
1 0
Y

A s-a-1 A Y
A Y A Y
0 1
X 1 1 D
Y 1 0

Buffer
A Y
A s-a-0 A Y A Y
0 0
X 0 1 D
1 1
Y
A Y
A s-a-1 A Y A Y
0 0
X 1 0 D
1 1
Y

ECE16 VLSI Testing and Verification VIII Semester

Propagation D cube
 D cube represent the input/output behavior of a good and the faulty gate
 The symbol D may assume 0 or 1
 D takes the value opposite to D (1 or 0)
 The definition of D and D could be interchanged, but they should be consistent
through out the circuit
 To obtain propagation D cube intersect two rows (singular cubes) of opposite
values
AND gate
A B Y A B Y
0 X 0 D 1 D
X 0 0 1 D D
1 1 1

OR Gate A B Y A B Y
0 0 0 D 0 D
1 X 1 0 D D
X 1 1

ECE16 VLSI Testing and Verification VIII Semester

Cont.

A B Y A B Y
0 X 1 D 1 D
X 0 1 1 D D
1 1 0

A B Y A B Y
0 0 1 D 0 D
1 X 0 0 D D
X 1 0

A Y A Y
0 1 D D
1 0

A Y A Y
0 0 D D
1 1

ECE16 VLSI Testing and Verification VIII Semester

 Test generation steps using D-algorithm
• Step 1. Select a pdcf for the given fault.
• Step 2. Drive the D (or D’ ) from the output of the gate
under test to an output of the circuit by successively
intersecting the current test cube with the
propagation D-cubes of successive gates. A test cube
represents the signal values at various lines in the
circuit during each step of the test generation process.
The intersection of a test cube with the propagation D-
cube of a successor gate results in a test cube.
• Step 3. Justify the internal line values by driving back
toward the inputs of the circuit, assigning input values
to the gates so that a consistent set of circuit input
values may be obtained.
Cont.

AND OR NAND NOR NOT Buffer

A B Y A B Y A B Y A B Y A Y A Y
l ar
u 0 X 0 0 0 0 0 X 1 0 0 1 0 1 0 0
i ng bes
S u X 0 0 1 X 1 X 0 1 1 X 0 1 0 1 1
C
1 1 1 X 1 1 1 1 0 X 1 0
NOT Buffer
AND s-a-0 OR s-a-0 NAND s-a-0 NOR s-a-0 s-a-0
s-a-0
A B Y A B Y A B Y A B Y
A Y A Y
1 1 D 1 X D 0 X D 0 0 D
0 D 1 D
DCF AND s-a-1 X 1 D X 0 D NOR s-a-1
P NOT Buffer
A B Y OR s-a-1 NAND s-a-1 A B Y s-a-1 s-a-1
0 X D A B Y A B Y 1 X D A Y
A Y
X 0 D 0 0 D 1 1 D X 1 D 1 D
0 D
NOT D-Intersection
AND OR NAND NOR A Y
A B Y A B Y A B Y A B Y D D
C D 1 D D 0 D D 1 D D 0 D Buffer
PD
1 D D 0 D D 1 D D 0 D D A Y
D D

ECE16 VLSI Testing and Verification VIII Semester

Cont.
Find the test vector using D-algorithm. PDCF NAND for s-a-0 fault
A C A B Y
G1 G2 D 0 X D
B
 s-a-0 X 0 D
PDC NOT
A Y
D D

A B C D
X X X X
PDCF of G1 for generating fault  s-a-0 0 X D X
0 X D X
PDC of G2 TO propagate fault X X D D
0 X D D
Consistency check 0 X D D

ECE16 VLSI Testing and Verification VIII Semester

Cont.

AND OR NAND NOR NOT Buffer

A B Y A B Y A B Y A B Y A Y A Y
l ar
u 0 X 0 0 0 0 0 X 1 0 0 1 0 1 0 0
i ng bes
S u X 0 0 1 X 1 X 0 1 1 X 0 1 0 1 1
C
1 1 1 X 1 1 1 1 0 X 1 0
NOT Buffer
AND s-a-0 OR s-a-0 NAND s-a-0 NOR s-a-0 s-a-0
s-a-0
A B Y A B Y A B Y A B Y
A Y A Y
1 1 D 1 X D 0 X D 0 0 D
0 D 1 D
DCF AND s-a-1 X 1 D X 0 D NOR s-a-1
P NOT Buffer
A B Y OR s-a-1 NAND s-a-1 A B Y s-a-1 s-a-1
0 X D A B Y A B Y 1 X D A Y
A Y
X 0 D 0 0 D 1 1 D X 1 D 1 D
0 D
NOT D-Intersection
AND OR NAND NOR A Y
A B Y A B Y A B Y A B Y D D
C D 1 D D 0 D D 1 D D 0 D Buffer
PD
1 D D 0 D D 1 D D 0 D D A Y
D D

ECE16 VLSI Testing and Verification VIII Semester

Cont.
Find the test vector using D-algorithm. A B Y
PDCF NAND
A s-a-1
E 1 1 D
G3
 s-a-1 A B Y
B G1
G PDC NAND D 1 D
D G4
1 D D

C G2 A Y
F Singular
0 1
Cube NOT
1 0

A B C D E F G
X X X X X X X
PDCF of G3 for generating fault  s-a-1 1 X X 1 D X X
1 X X 1 D X X
PDC of G4 to propagate fault X X X X D 1 D
1 X X 1 D 1 D
Consistency check (G1) X 0 X X X X X
1 0 X 1 D 1 D
Consistency check (G2) X X 0 X X X X
1 0 0 1 D 1 D

ECE16 VLSI Testing and Verification VIII Semester

Cont.

AND OR NAND NOR NOT Buffer

A B Y A B Y A B Y A B Y A Y A Y
l ar
u 0 X 0 0 0 0 0 X 1 0 0 1 0 1 0 0
i ng bes
S u X 0 0 1 X 1 X 0 1 1 X 0 1 0 1 1
C
1 1 1 X 1 1 1 1 0 X 1 0
NOT Buffer
AND s-a-0 OR s-a-0 NAND s-a-0 NOR s-a-0 s-a-0
s-a-0
A B Y A B Y A B Y A B Y
A Y A Y
1 1 D 1 X D 0 X D 0 0 D
0 D 1 D
DCF AND s-a-1 X 1 D X 0 D NOR s-a-1
P NOT Buffer
A B Y OR s-a-1 NAND s-a-1 A B Y s-a-1 s-a-1
0 X D A B Y A B Y 1 X D A Y
A Y
X 0 D 0 0 D 1 1 D X 1 D 1 D
0 D
NOT D-Intersection
AND OR NAND NOR A Y
A B Y A B Y A B Y A B Y D D
C D 1 D D 0 D D 1 D D 0 D Buffer
PD
1 D D 0 D D 1 D D 0 D D A Y
D D

ECE16 VLSI Testing and Verification VIII Semester

Cont.
Find the test vector using D-algorithm. A Y
 s-a-0 PDCF BUFFER
A D s-a-1 1 D
G1
B F A B Y
G3
C PDC NOR D 0 D
G2 E 0 D D
A  s-a-0
Z
G1
D A B Y
B F D 1 D
G3 PDC NAND
C 1 D D
G2 E
Z A B C D E F Singular
X X X X X X X Cube NOT
PDCF of buffer for  s-a-0 1 D X X X X X
1 D X X X X X A Y
PDC of G1 to propagate fault X D 0 X D X X 0 1
1 D 0 X D X X 1 0
PDC of G3 to propagate fault D 1 D
X X X X D 1 D
1 D 0 X D 1 D
Consistency check (G2) X X X 0 X X X
1 D 0 0 D 1 D

ECE16 VLSI Testing and Verification VIII Semester

Cont.

AND OR NAND NOR NOT Buffer

A B Y A B Y A B Y A B Y A Y A Y
l ar
u 0 X 0 0 0 0 0 X 1 0 0 1 0 1 0 0
i ng bes
S u X 0 0 1 X 1 X 0 1 1 X 0 1 0 1 1
C
1 1 1 X 1 1 1 1 0 X 1 0
NOT Buffer
AND s-a-0 OR s-a-0 NAND s-a-0 NOR s-a-0 s-a-0
s-a-0
A B Y A B Y A B Y A B Y
A Y A Y
1 1 D 1 X D 0 X D 0 0 D
0 D 1 D
DCF AND s-a-1 X 1 D X 0 D NOR s-a-1
P NOT Buffer
A B Y OR s-a-1 NAND s-a-1 A B Y s-a-1 s-a-1
0 X D A B Y A B Y 1 X D A Y
A Y
X 0 D 0 0 D 1 1 D X 1 D 1 D
0 D
NOT D-Intersection
AND OR NAND NOR A Y
A B Y A B Y A B Y A B Y D D
C D 1 D D 0 D D 1 D D 0 D Buffer
PD
1 D D 0 D D 1 D D 0 D D A Y
D D

ECE16 VLSI Testing and Verification VIII Semester

40
Problem
Find the test vector using D-algorithm.

s-a-1

Test Vector : AB = 11

ECE16 VLSI Testing and Verification VIII Semester

Problem
Find the test vector using D-algorithm.

B F
G1
C G4
I
G3
H
D G2 s-a-0
E G

Test Vector : ABCDE = 01100

ECE16 VLSI Testing and Verification VIII Semester

Cont.

AND OR NAND NOR NOT Buffer

A B Y A B Y A B Y A B Y A Y A Y
l ar
u 0 X 0 0 0 0 0 X 1 0 0 1 0 1 0 0
i ng bes
S u X 0 0 1 X 1 X 0 1 1 X 0 1 0 1 1
C
1 1 1 X 1 1 1 1 0 X 1 0
NOT Buffer
AND s-a-0 OR s-a-0 NAND s-a-0 NOR s-a-0 s-a-0
s-a-0
A B Y A B Y A B Y A B Y
A Y A Y
1 1 D 1 X D 0 X D 0 0 D
0 D 1 D
DCF AND s-a-1 X 1 D X 0 D NOR s-a-1
P NOT Buffer
A B Y OR s-a-1 NAND s-a-1 A B Y s-a-1 s-a-1
0 X D A B Y A B Y 1 X D A Y
A Y
X 0 D 0 0 D 1 1 D X 1 D 1 D
0 D
NOT D-Intersection
AND OR NAND NOR A Y
A B Y A B Y A B Y A B Y D D
C D 1 D D 0 D D 1 D D 0 D Buffer
PD
1 D D 0 D D 1 D D 0 D D A Y
D D

ECE16 VLSI Testing and Verification VIII Semester

Problem
Find the test vector using D-algorithm.

Test Vector : ABC = 011

ECE16 VLSI Testing and Verification VIII Semester

Cont.

AND OR NAND NOR NOT Buffer

A B Y A B Y A B Y A B Y A Y A Y
l ar
u 0 X 0 0 0 0 0 X 1 0 0 1 0 1 0 0
i ng bes
S u X 0 0 1 X 1 X 0 1 1 X 0 1 0 1 1
C
1 1 1 X 1 1 1 1 0 X 1 0
NOT Buffer
AND s-a-0 OR s-a-0 NAND s-a-0 NOR s-a-0 s-a-0
s-a-0
A B Y A B Y A B Y A B Y
A Y A Y
1 1 D 1 X D 0 X D 0 0 D
0 D 1 D
DCF AND s-a-1 X 1 D X 0 D NOR s-a-1
P NOT Buffer
A B Y OR s-a-1 NAND s-a-1 A B Y s-a-1 s-a-1
0 X D A B Y A B Y 1 X D A Y
A Y
X 0 D 0 0 D 1 1 D X 1 D 1 D
0 D
NOT D-Intersection
AND OR NAND NOR A Y
A B Y A B Y A B Y A B Y D D
C D 1 D D 0 D D 1 D D 0 D Buffer
PD
1 D D 0 D D 1 D D 0 D D A Y
D D

ECE16 VLSI Testing and Verification VIII Semester

PODEM (Path Oriented Decision Making)
 PODEM is an enumeration (complete) algorithm in which all patterns are
examined as tests for a given fault
 The search for a test continues until the search space is exhausted or a test
pattern is found
 If no test pattern is found, the fault is considered to be undetectable
 In D-algorithm, line justification, i.e., line values assigned during the
backtracking toward the inputs of the circuit, allows assignments on any
internal lines
 In PODEM, backtracking is allowed on primary inputs only, thus reducing the
number of backtracks

ECE16 VLSI Testing and Verification VIII Semester

47
Cont.
PODEM consists of six steps:
 Step 1. Assume all primary inputs are x, which are unassigned. Determine an
initial objective; an objective is defined by a logic (0 or 1) value referred to as
objective logic level. The initial objective is to select a logic value so that the
fault to be detected is sensitized.
 Step 2. Select a primary input and assign a logic value that has good likelihood
of satisfying the initial objective.
 Step 3. Propagate forward the value at the selected primary input in
conjunction with X’s at the rest of the primary inputs by using the five-valued
logic 0, 1, X, D, and D
 Step 4. If it is a test, a D or a D is propagated to the output of the circuit, exit;
otherwise, assign the complement of the previous value to the primary input
and determine whether it is a test.

ECE16 VLSI Testing and Verification VIII Semester

Cont.

 Step 5. Assign a 0 or a 1 to one more primary input, and go to step 4 to check

whether the resulting combination is a test.
 Step 6. Continue with steps 4 and 5 until a test is found, or the fault is found to
be undetectable.

 The main difference between PODEM and D-Algorithm are as follows

 In PODEM, backtracking is allowed only on primary inputs not on any
internal line.
 PODEM does not require the consistency check operation.
 the D-algorithm can lead to a waste of effort if a given fault is untestable.
Thus, PODEM is more efficient than the D-algorithm in terms of computer
time required to generate tests for combinational circuits.

ECE16 VLSI Testing and Verification VIII Semester

Example-1
 Let us derive a test for fault l s-a-1

s-a-1

 Since a test for fault l s-a-1 is to be derived, the initial objective is to set l to 0
 Either B or C can be assigned 1 to satisfy the objective
 Assuming we choose B to be at 1, the result of the forward propagation is

A B C l m n p F A B Y
1 X D
X 1 X D 0 X X X X 1 D

ECE16 VLSI Testing and Verification VIII Semester

Cont.

s-a-1

A B C l m n p F
X 1 X D 0 X X X
 The next objective is to propagate D through n to output F. This can be done by
assigning a proper logic value to C. If C = 1, propagation of D is blocked, hence
C=0
A B Y
A B C l m n p F D 0 D
X 1 0 D 0 D D X 0 D D
 The final objective is to propagate D to output F. This can be done by assigning
A=0

A B C l m n p F Test Vector ABC=010

0 1 0 D 0 D D D

ECE16 VLSI Testing and Verification VIII Semester

Example-2
a j AND s-a-0 OR AND
G3
b A B Y
l A B Y A B Y
c h s-a-0 G5 1 1 D
d G1 D 0 D D 1 D
G4 0 D D 1 D D
k
e
G2
f i
m
g G6
 Set h = 1
a b c d e f g h i j k l m
X X 1 1 X X X D X X X X X
 To propagate through G4, i=0, e = f = 1 (already d = 1)

a b c d e f g h i j k l m
X X 1 1 1 1 X D 0 X D X X
 To propagate through G5, j =1, a=1 or b=1

a b c d e f g h i j k l m
1 X 1 1 1 1 X D 0 1 D D X
 Test Vector: a b c d e f g = 1X1111X

ECE16 VLSI Testing and Verification VIII Semester

 Example-2
The derivation of a test for fault α s-a-0 in the circuit
shown using PODEMEEExample-2

53
The initial objective is to set the
output of gate A to logic 1; that is,
the objective logic level is 1 on net.
Both primary inputs x1 and x2 drive
gate A.

54
Thus, the test for the fault α s-a-0 is x1x2x3x4=0000.
55
Problem
 Find test vector for F s-a-1 fault by using PODEM

A F s-a-1
G2

G4 G
B
G1 G3
C D E

 Test Vector: ABC = 01X or 0X1

ECE16 VLSI Testing and Verification VIII Semester

• PODEM proves to be more efficient as
compared to a D-ALG because it limits its
search space only to Primary Inputs (PIs) of
the circuits. D-ALG on the other hand has a
search space comprising of all the internal
nodes of the circuit along with the PIs.

57
 FAN
Several terms have to be defined before discussing the
test generation process used by FAN:
• bound line: a gate output that is part of a
reconvergent fan-out loop.(i.e the line fed
directly or indirectly by fanout stem)
• free line: one that is not bound is
considered to be free line
• headline: a free line that is either:
(i) fanout stem
(ii) input to a gate with bound output
58
To identify bound line, free line and head
line in the given circuit

bound line: the line fed directly (I, j) or indirectly (m) by fanout stem)

free line: one that is not bound, a to f, h, j

headline: a free line that is either:

(i) fanout stem (j)
(ii) input to a gate with bound output (h)

59
60
FAN
 The FAN algorithm is in principle similar to PODEM but is made more efficient by
reducing the number of backtracks
 FAN uses a technique called multiple backtracks to reduce the number of
backtracks that must be made during the search process
 Example E=1

C=0
F=1 H=1

G=0 H=0

 in Figure shown, if the objective is to set H at logic 1, PODEM would backtrack

along one of the paths to the primary inputs
 Suppose the backtrack is done via the path H-E-C, to set E to 1, C will set to 0.
However a 0 at C sets F to 1, G to 0, and H to 0

ECE16 VLSI Testing and Verification VIII Semester

Cont.
E=1
B=0
C=1
F=0
H=1

G=1
 Since this assignment fails to achieve the desired objective, the backtrack
process is performed via another path, for example, H−G−F−C
 Thus, in PODEM, several backtracks may be necessary before the requirement
of setting up a particular logic value on a line is satisfied.
 FAN avoids this waste of computation time by backtracking along multiple
paths to the fan-out point
 If multiple backtrack is done via both H−E−C and H−G−F−C, the value at C
can be set so that the value at H is justified
 In PODEM, a logic value assigned to a primary input in order to achieve one
objective may in turn result in the failure of satisfying another objective,
thereby forcing a backtrack

ECE16 VLSI Testing and Verification VIII Semester

Cont.
 Example
G=1
A=1
B=1
M=1
Z=1

E=1 N=1
F=1
I=1

 Application of the FAN algorithm to derive a test for the fault Z s-a-0
 First, the value D is assigned to the line Z and the value 1 to each of the inputs
M and N. The initial objectives are to set M and N to 1
 By the multiple backtrack, G and I are assigned 1 (note that instead of G and I,
L could be assigned logic 1).
 Again, by the multiple backtrack, we have the final objectives A=l, B=l and
E=1, F=l.

ECE16 VLSI Testing and Verification VIII Semester

Cont.
 Example

G=1
A=1
B=1
M=1
Z=1

E=1 N=1
F=1
I=1

 The assignment A=1, B=l makes J=1, M=1, and the assignment E=1, F=1
makes I=1, N=1. Thus, the assignments A=B=E=F=1 constitute a test for the
fault Z s-a-0.
 If the first multiple backtracks stopped at L and the second multiple backtrack
at H, the test for the fault would be C=D=1.

ECE16 VLSI Testing and Verification VIII Semester

Problem

A=0 G G=0
I=1

s-a-0
H=0
E=0
F=0
J=1

 Test Vector: ABCDEF = 0XXX00

ECE16 VLSI Testing and Verification VIII Semester

Recap
 Test generation for combinational logic circuits
 Truth Table and fault matrix
 Path sensitization
 D – Algorithm
 Singular Cubes
 D – Intersection
 Primitive D cube of a fault (PDCF)
 Propagation D cube
 PODEM
 FAN

ECE16 VLSI Testing and Verification VIII Semester