UNIT-4

Digital Electronics: Number system & representation. Introduction of Basic and

Universal Gates, using Boolean algebra simplification of Boolean function. K Map
Minimization upto 6 Variable.
 Logic Gates-

Logic gates can be broadly classified as-

Basic Logic Gates-

Basic Logic Gates are the fundamental logic gates using

which universal logic gates and other logic gates are
constructed.

They have the following properties-

Basic logic gates are associative in nature.
Basic logic gates are commutative in nature.

There are following three basic logic gates-

AND Gate
OR Gate
NOT Gate
1. AND Gate-

The output of AND gate is high (‘1’) if all of its inputs are high (‘1’).
The output of AND gate is low (‘0’) if any one of its inputs is low (‘0’).

Logic Symbol-

The logic symbol for AND Gate is as shown below-

2. OR Gate-

The output of OR gate is high (‘1’) if any one of its inputs is high (‘1’).
The output of OR gate is low (‘0’) if all of its inputs are low (‘0’).

Logic Symbol-

The logic symbol for OR Gate is as shown below-

3. NOT Gate-

The output of NOT gate is high (‘1’) if its input is low (‘0’).
The output of NOT gate is low (‘0’) if its input is high (‘1’).

From here-
It is clear that NOT gate simply inverts the given input.
Since NOT gate simply inverts the given input, therefore it is also known
as Inverter Gate.
Universal Logic Gates-

They are called as “Universal Gates” because-

•They can realize all the binary operations.
•All the basic logic gates can be derived from them.

Universal logic gates are the logic gates that are capable of
implementing any Boolean function
without requiring any other type of gate.

They have the following properties-

Universal gates are not associative in nature.
Universal gates are commutative in nature.

There are following two universal logic gates-

NAND Gate
NOR Gate

1. NAND Gate-

A NAND Gate is constructed by connecting a NOT Gate at the output

terminal of the AND Gate.
The output of NAND gate is high (‘1’) if at least one of its inputs is low (‘0’).
The output of NAND gate is low (‘0’) if all of its inputs are high (‘1’).
2. NOR Gate-

A NOR Gate is constructed by connecting a NOT Gate at the output terminal

of the OR Gate.
The output of OR gate is high (‘1’) if all of its inputs are low (‘0’).
The output of OR gate is low (‘0’) if any of its inputs is high (‘1’).

Logic Symbol-

The logic symbol for NOR Gate is as shown below-

Ex-OR

An odd number of logic “1’s” on its inputs gives a logic “1” at the output.
These two inputs can be at logic level “1” or at logic level “0” giving us
the Boolean expression of:
Q = (A ⊕ B) = A.B’ + A’.B
Ex-NOR

An Even number of logic “1’s” on its inputs gives a logic “1” at the output.
These two inputs can be at logic level “1” or at logic level “0” giving us
the Boolean expression of:
Q = (A ⊕ B) = A.B + A’.B’
Using Boolean algebra simplification of Boolean function

Rule-1

Rule-2
x + xy =x
Similarly there are other property which can prove but we will remember only without
proving.

A+BC=(A+B)(A+C)

Most commonly used property for minimizing Boolean function are

Circuit simplification example

AB+BC(B+C)=B(A+C)
A+B(A+C)+AC=A+BC
A+B(A+C)+AC=?
DE MORGAN THEOREM

DeMorgan’s theorems state the same equivalence in “backward” form: that inverting
the output of any gate results in the same function as the opposite type of gate (AND
vs. OR) with inverted inputs:

DeMorgan’s First theorem proves that when two (or more) input variables
are AND’ed and negated, they are equivalent to the OR of the complements of the
individual variables. Thus the equivalent of the NAND function will be a negative-OR
function, proving that A.B = A+B. We can show this operation using the following table
DeMorgan’s Second Theorem
DeMorgan’s Second theorem proves that when two (or more) input variables
are OR’ed and negated, they are equivalent to the AND of the complements of
the individual variables. Thus the equivalent of the NOR function is a negative-
AND function proving that A+B = A.B, and again we can show operation this
using the following truth table.
 Karnaugh Maps

• Karnaugh maps (K-maps) are graphical representations of

Boolean functions.
• One map cell corresponds to a row in the truth table.
• Also, one map cell corresponds to a minterm or a maxterm in
the Boolean expression
• Multiple-cell areas of the map correspond to standard terms.
• A K-map provides a systematic method for simplifying Boolean
expressions and, if properly used, will produce the simplest SOP
or POS expression possible, known as the minimum expression.
 What is K-Map

• It’s similar to truth table; instead of being organized

(i/p and o/p) into columns and rows, the K-map is an
array of cells in which each cell represents a binary
value of the input variables.
• The cells are arranged in a way so that simplification
of a given expression is simply a matter of properly
grouping the cells.
• K-maps can be used for expressions with 2, 3, 4, and
5 variables.
 Two-Variable Map

• Any two adjacent cells in the map differ by ONLY one variable,
which appears complemented in one cell and
uncomplemented in the other.
• Example:
m0(=x1’x2’) is adjacent to m1(=x1’x2) and m2(=x1x2’) but NOT m3
(=x1x2)
 Cell Adjacency
CD
00 01 11 10
AB
00
01
11
10
 K-Map SOP Minimization

• The K-Map is used for simplifying Boolean expressions to their

minimal form.
• A minimized SOP expression contains the fewest possible
terms with fewest possible variables per term.
• Generally, a minimum SOP expression can be implemented
with fewer logic gates than a standard expression.
 Grouping
Rules of grouping -

1’s & 0’s can

not be grouped

diagonal 1’s can

not be grouped
Elements in a group should be 2n
 Minimum
Groups
should be
formed

For above
rule group
Overlapping
is applicable
Mapping Directly from a Truth Table
I/P O/
P C
A B C X 0 1
AB
0 0 0 1
0 0 1 0 00 1
0 1 0 0
0 1 1 0 01
1 0 0 1 11 1 1
1 0 1 0
1 1 0 1 10 1
1 1 1 1
 Don’t Care Conditions

• A don’t care condition, marked by (X) in the truth

table, indicates a condition where the design
doesn’t care if the output is a (0) or a (1).
• A don’t care condition can be treated as a (0) or a (1)
in a K-Map.
• Treating a don’t care as a (0) means that you do not
need to group it.
• Treating a don’t care as a (1) allows you to make a
grouping larger, resulting in a simpler term in the SOP
equation.
 Example
Solution:
R S T U F4
0 0 0 0 X
0 0 0 1 0 V
0 0 1 0 1
0 0 1 1 X
0 1 0 0 0
0 1 0 1 X
0 1 1 0 X
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 X
1 1 0 0 X
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
 K-Map POS Minimization

• The approaches are much the same (as SOP) except that with
POS expression, 0s representing the standard sum terms are
placed on the K-map instead of 1s.
 Design of combinational digital circuits

• Steps to design a combinational digital circuit:

– From the problem statement derive the truth table

– From the truth table derive the unsimplified logic

expression

– Simplify the logic expression

– From the simplified expression draw the logic circuit

Example: Design a 3-input (A,B,C) digital circuit that will give at its output
(X) a logic 1 only if the binary number formed at the input has more ones
than zeros.

Inputs Output
A B C X X (3,5,6,7)
0 0 0 0 0
X
1 0 0 1 0 BC
2 0 1 0 0 A 00 01 11 10
3 0 1 1 1 0 0 0 1 0
4 1 0 0 0 1 0 1 1 1
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1 X  AC  AB BC
A B C