Design Technologies for Integrated Systems

Giovanni De Micheli
Integrated Systems Laboratory

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© Giovanni De Micheli – All rights reserved
 Course objectives

A state-of-the art “chip” (integrated circuit) consists of up

to trillions of transistors
These are designed using Electronic Design Automation
(EDA) tools
In this course you will:
 Understand the inner workings of (some) EDA tools
 Models and algorithms
 How to use them effectively to design digital hardware

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 Module 1

 Objective
 Electronic systems and their requirements
 Integrated circuits
 Design styles

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 Computing today

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 Computing today

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 The Internet of Things

Infrastructural
Core

Sensory
swarm

Mobile
access
(c) Giovanni De Micheli [Courtesy: J. Rabaey]
 Requirements for electronic chip design

Mobility Life critical Complex Sw

Ultra low power High reliability High performance

Low voltage Redundancy Parallelism

 From processors to multi-processors

 Clock speed limitaions
 Performance gain from parallelism

[Tilera]
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 New communication structures

 Design requirements:
 Predictable design
 Fast design closure

 Network on Chip communication

[Vangal, Intel07]
 Modular and flexible interconnect
 Reliable on-chip communication
 Structured design with synthesis and optimization support

NoC
NoC
Packets Models
Blocks
Routes
IP Cores
Topology FPGA
Comm Back
Graph Synthesis Topology
NoC End
Generation Flow
PE Network ASIC
Floorplan
Interface Constraints
Goals
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 Systems on Chip

 Large-scale
 Billion transistor chips
 Multi-cores, multi-threaded sw
 Power-consumption limited
 Dark silicon
 Very expensive to design
 Non recurring engineering (NRE) costs
NVIDIA TEGRA Processor
 Migration toward software

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 Wafer scale integration (Cerebras)

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 Systems in Package

 There is a diminishing return in integrating everything on Silicon

 Heterogeneous technologies
 Multiple voltages
 Thermal issues
 Packaging technology

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 New packaging technology

 From planar to 3D integration

 Chips have limited wiring resources

[Fraunhofer]
 Electrical and manufacturing constraints limit
heterogeneous planar integration

 Through silicon vias allow designer to stack:

 Computing arrays
 Memory arrays
 Analog and RF circuitry

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NVidia 2.5D-IC High BW Memory Application

15 mm
8
GP U mm
2

00
1,4
r ( s)
r pose
n Inte
o
Silic
GPU Die (21B Transistors @ 12 Nanometers TSMC, 300W) + 4 HBM2 Stacks (4  4GB) Onto
Several Silicon Interposer“Volta”
Die Stitched Together, price at launch $10,000
5.5D-IC (3D + 2.5D) Integration; Source: J.-H. Huang, et al., NVIDIA, GPU Technology Conference 2017

Credit: Stanford EE292A Lecture 1

 The emerging nano-technologies
 Enhanced silicon CMOS is likely to remain the
main manufacturing process in the medium term
 The 3nm technology node is here (2022)
 What are the candidate techs
for the 3nm node and beyond?
 Silicon Nanowires/sheets (SiNW))
 Carbon Nanotubes (CNT)
 2D devices (flatronics)
 What is in common from a design standpoint?

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 22 nm Tri-Gate Transistors

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[Courtesy: M. Bohr]
 Fully Depleted SoI Transistors

[Courtesy: STMicroelectronics]

 Transistor is built on top of buried oxide (BOX)

 Thin, undoped channel (fully depleted)
 Fine power-consumption control through body bias
 Silicon Nanowire Transistor

 Fully compatible with CMOS process

 Gate all around
 High Ion / Ioff ratio

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FINFETs, NanoWires and NanoSheets

[INTEL, 2017]
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 Carbon Nanotube Transistors

 CNTs benefit from higher mobility and thus higher currents

 CNTs grown separately but can be ported to Si wafers
 Handling CNT imperfections is major design and fabrication issue

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 CNT nanocomputer

 First CNT computing engine

 Runs 20 MIPS instructions
 Multitasking

[Shulaker, Wong, Mitra et al, NatureNano 13]

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16B RISC-V 14’000 CNFET transistor chip

[Shulaker et al., Nature 19]

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 2D electronic technologies

[Kis, Nature Nano 2011]

 Graphene, MoS2 and other materials
 Single or few atomic layers
 High Ion / Ioff ratio for MoS2 (108) but n-type mainly
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 MoS2 nanocomputer

 First MoS2 computing engine

 Runs 4instructions
 115 N-xtors (enhancement load)
 2 micron feature size

[Wacter et al. Nature Comm, 2017]

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 Controllable polarity transistors in 2D

2D Controllable-polarity EXOX in WSe2

[Resta, ACS Nano 2017]

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Quantum computing technologies

A wide array of realization technologies

Superconductors, silicon, optics

QC leverages superposition and entanglement

Support algorithms with lower complexity

Scaling and noise are still issues

Qubit count and coherence time are limited

Refrigeration to tenth of mK for noise reason

Interfacing to host is complex

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 Integrated Circuit Design Styles

 Custom:
 All geometries are designed ad hoc
 Mainly abandoned, but useful for high-performance components

 Semicustom:
 Optimality is traded-off for regularity
 Performance penalty is small, cost is lower

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 The Custom Approach

Intel 4004

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Courtesy Intel
 Transition to Automation and Regular Structures

Intel 4004 (‘71)

Intel 8080 Intel 8085

Intel 8286 Intel 8486

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Courtesy Intel
 Standard Cell - Example

3-input NAND cell

(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time

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 Cell-based Design (or standard cells)

Routing channel
requirements are
reduced by presence
of more interconnect
layers

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 Standard Cell – The New Generation

Cell-structure
hidden under
interconnect layers

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 “Soft” MacroModules

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Synopsys DesignCompiler
 Gate Array — Sea-of-gates

polysilicon

VD D

metal
rows of Uncommited
uncommitted possible
cells GND contact Cell

In 1 In 2 In 3 In4

routing
channel Committed
Cell
(4-input NOR)
Out

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 Field-Programmable Gate Arrays
Fuse-based

Standard-cell like
floorplan
I/O Buffers

P rogram/ Tes t/D iag nosti cs

Verti cal ro utes
I/O Buffers

I/O Buffers
R ow s o f logi c m odule s
R outi ng c hannel s

I/O Buffers

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 Field Programmable Gate Arrays
Xilinx LUT Architecture

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Courtesy Xilinx
 Heterogeneous Programmable Platforms
FPGA Fabric

Embedded memories
Embedded PowerPc

Hardwired multipliers

Xilinx Virtex-II Pro

High-speed I/O
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Courtesy Xilinx
 Integrated Circuit Design Styles

Digital Circuit Implementation Approaches

Custom Semicustom

Cell-based Array-based

Standard Cells Pre-diffused Pre-wired

Macro Cells
Compiled Cells (Gate Arrays) (FPGA's)

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 The Basic Trade-Offs

Cost [log]

Custom: Lowest cost/size at high volume, best performance

Semi-Custom: Slightly higher cost/size at volume, performance

SW: Highest flexibility

FPGA: High flexibility

chips/year [log]
Design Cost
(aka NRE)

Credit: Stanford EE292A Lecture 1

 Moore’s law

Source: Gordon E. Moore,

Cramming More Components onto Integrated Circuits,
Electronics, pp. 114–117, April 19, 1965.

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End of Moore’s Law?
 8 Generations of Apple Mobile
System-on-Chips

Chip A4 A5 A6 A7 A8 A9 A10 A11

Year 2010 2011 2012 2013 2014 2015 2016 2017
Device iPhone iPhone iPhone iPhone iPhone iPhone iPhone iPhone
4 4s 5 5s 6 6s 7 8&X

Node 45nm 45nm 32nm 28nm 20nm 16nm/14nm 16nm 10nm

Samsung Samsung Samsung Samsung TSMC TSMC/Samsung TSMC TSMC
Area 0.52 1.25 0.96 1.03 0.89 1.05/0.96 1.25 0.88
[cm2]

Die photos: chipworks/TechInsights

Data source: wikipedia
 Module 2

 Objective
 Electronic design automation
 Synthesis and optimization
 Multi-criteria optimization

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 Computer-aided design

 Enabling design methodology

 Support large scale system design
 Design optimization, centering and trade-off
 Reduce design time and time to market
 … the only purpose of science is to ease the hardship of
human existence … [Galileo/Brecht]

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 Microelectronic circuit design

 Conceptualization and modeling

 Hardware description languages
 Synthesis and optimization
 Model refinement
 Validation
 Check for correctness

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 Synthesis history

 Few logic synthesis algorithms and tools existed in the 70’s

 Link to place and route for automatic design

 Innovative methods at IBM, Bell Labs, Berkeley, Stanford
 First prototype synthesis tools in the early 80s
 YLE [Brayton], MIS [Berkeley], Espresso
 First logic synthesis companies in the late 80’s
 Synopsys and others

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 Modeling abstractions

 Architectural level
 Operations implemented by resources
 Logic level
 Logic functions implemented by gates
 Geometrical level
 Transistors and wires

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 Circuit synthesis

 Architectural-level synthesis
 Determine macroscopic structure
 Interconnection of major building blocks

 Logic-level synthesis
 Determine the microscopic structure
 Interconnection of logic gates

 Physical design
 Geometrical-level synthesis
 Determine positions and connections

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 Synthesis levels

b-view s-view

a-synthesis
a-level

l-synthesis
l-level

p-design
g-level

p-view

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 Synthesis and optimization
 Synthesis with no optimization has no value
 Optimization is the means to outperform manual design
 Objectives
 Performance
 Frequency, latency, throughput
 Energy consumption
 Area (yield and packaging cost)

 Testability, dependability, …

 Optimization has multiple objectives

 Trade off

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 Combinational circuit optimization

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 Optimization trade-off in sequential circuits
Area

Area

Area

Area
Max

e
tim
l e-
c
Cy
Latency

Latency

Latency
Latency
Max

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 Pareto points

 Multi-criteria optimization

 Multiple objectives

 Pareto point:
 A point of the design space is a Pareto point if there is no other
point with:
 At least one inferior objectives
 All other objectives inferior or equal

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 Example
Differential equation solver

diffeq {
read ( x, y, u, dx, a ) ;
repeat {
xl = x + dx;
ul = u – ( 3 . x . u . dx ) – ( 3 . y . dx ) ;
yl = y + u . dx ;
c=x<a;
x = xl; u = ul; y = yl ;
until ( c );
write ( y )
}

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 Example

STEERING CONTROL
ALU
* & UNIT
MEMORY

STEERING CONTROL
ALU
* ALU
* &
MEMORY
UNIT

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 Example

Area

15
(2,2)
13 (2,1)
12

10

8 X(1,2)
7 (1,1)
5

Latency

1 2 3 4 5 6 7 8

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 Summary

 Computer-aided IC design methodology:

 Capture design by HDL models
 Synthesize more detailed abstractions

 Optimize circuit parameters

 Evolving scientific discipline

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