8086 Microprocessor Architecture

Features of 8086 Microprocessor

The 8086 microprocessor has several key features that differentiate it from earlier processors:
•16-bit Processor: The ALU (Arithmetic Logic Unit), internal registers, and data bus are all 16-
bit, allowing it to process 16-bit data at a time.
•20-bit Address Bus: Can address up to 1MB (220^2020) of memory using a segmented
memory model.
•Instruction Queue (Pipelining): A 6-byte prefetch queue allows instruction fetching to
overlap with execution, improving speed.
•Operating Modes: Supports both minimum mode (single processor) and maximum mode
(multiprocessor system) operations.
•Registers: Includes general-purpose registers, segment registers, pointer registers, and index
registers.
•Memory Segmentation: Uses segmented addressing, where memory is divided into 64KB
segments (Code, Data, Stack, Extra).
•Interrupt Handling: Supports 256 interrupts, including both hardware and software
interrupts.
•Clock Speed: Available in 5 MHz, 8 MHz, and 10 MHz versions.
•Multiplication and Division Support: Can perform multiplication and division operations
internally.
•I/O Addressing: Supports I/O-mapped I/O (64K ports) and memory-mapped I/O
Execution Unit (EU):
• Contains general-purpose registers (AH, AL, BH, BL, CH, CL, DH, DL) and
special-purpose registers (SP, BP, SI, DI).
• Includes the Arithmetic and Logic Unit (ALU), responsible for arithmetic
and logical operations.
• Uses temporary registers for intermediate calculations.
• Has a flags register, which stores the status of operations.
• The Execution Unit Control System manages operations and interacts
with the Bus Interface Unit.
Bus Interface Unit (BIU):
• Contains segment registers (CS, DS, SS, ES) and the instruction pointer
(IP).
• Has an instruction queue for pipelining, allowing prefetching of
instructions for faster execution.
• Uses an adder to compute the 20-bit address from segment and offset.
• Manages communication with memory and I/O using the external bus.
Execution Unit (EU)
• Bus Interface Unit (BIU)
• Each unit has specific responsibilities to ensure efficient instruction execution. Let's break it down:
• 1. Execution Unit (EU)
• The Execution Unit (EU) is responsible for executing instructions. It includes:
• a) General Purpose Registers
• The EU contains eight general-purpose registers divided into high (H) and low (L) parts:
– AH, AL → AX (Accumulator Register)
– BH, BL → BX (Base Register)
– CH, CL → CX (Count Register)
– DH, DL → DX (Data Register)
These registers are used for arithmetic, logical, and data manipulation operations.
• b) Special Purpose Registers
• SP (Stack Pointer) → Points to the top of the stack.
• BP (Base Pointer) → Used for stack-based addressing.
• SI (Source Index) & DI (Destination Index) → Used for string and memory operations.
• c) Arithmetic and Logic Unit (ALU)
• Performs arithmetic operations (addition, subtraction, etc.).
• Performs logical operations (AND, OR, XOR, etc.).
• d) Temporary Registers & Flags Register
• Temporary Registers: Used to hold intermediate results during computations.
• Flags Register: Stores the status of the last operation (Zero Flag, Carry Flag, etc.), which affects conditional execution.
• e) Execution Unit Control System
• Directs the flow of execution and interacts with the Bus Interface Unit (BIU).
2. Bus Interface Unit (BIU)
• The BIU is responsible for memory addressing and fetching instructions from memory. It consists of:
• a) Instruction Queue (Pipelining)
• The 8086 uses prefetching, where instructions are fetched in advance and stored in a 6-byte queue.
• This improves efficiency by reducing delays between instruction execution.
• b) Segment Registers
• The BIU uses segment registers to handle memory addressing efficiently:
• CS (Code Segment) → Holds the address of the code being executed.
• DS (Data Segment) → Holds the address of the data being used.
• SS (Stack Segment) → Holds the address of the stack.
• ES (Extra Segment) → Used for additional memory addressing.
• c) Instruction Pointer (IP)
• The IP register stores the address of the next instruction to be executed.
• d) Address Adder (Address Calculation)
• The 8086 generates a 20-bit physical address by combining a 16-bit segment address and an offset.
• This is done using an adder, allowing the processor to access 1MB of memory.
• e) Bus Control Logic
• Manages communication with external devices and memory via the External Bus.
• Handles data transfer between memory and the CPU using the 16-bit data bus.
Key Features of the 8086 Architecture in the Image
1. Pipelining: Instruction queue allows simultaneous fetching and execution.
2. 16-bit ALU: Performs arithmetic and logic operations efficiently.
3. Segmented Memory: Uses segment registers to access 1MB of memory.
4. 20-bit Address Bus: Enables access to a larger memory space.
5. 16-bit Data Bus: Transfers data between the CPU and memory.
Step-by-Step Execution:
1. BIU Fetches Instructions
1. The BIU fetches MOV AX, 1234H into the instruction queue.
2. Then, it fetches ADD AX, 5678H.
2. Instruction Decoding by EU
1. The EU decodes MOV AX, 1234H and sends a signal to load
1234H into AX.
2. Then, it decodes ADD AX, 5678H.
3. ALU Executes the Operation
1. The ALU adds 1234H + 5678H = 68ACH.
2. The result (68ACH) is stored in AX.
4. Flags are Updated
1. If the result was zero, ZF would be set.
2. If there was a carry, CF would be set.