Module 1

presentation 2
Parallelism in uniprocessor systems

 A uniprocessor (one CPU) system can perform two

or more tasks simultaneously. It is possible to
achieve parallelism with a uniprocessor
system.
Example :
▪ Instruction pipeline: An instruction pipeline reads
instruction from the memory while previous
instructions are being executed in other segments of
the pipeline. Thus we can execute multiple
instructions simultaneously
 Note that a system that performs different
operations on the same instruction is
not considered parallel. Only if the system
processes two different instructions
simultaneously can it be considered
parallel
Basic Uniprocessor Architecture :

 A typical uniprocessor computer consists of three major

components:
1. The main memory
2. The central processing unit (CPU)
▪ Set of general purpose registers along with
PC(Program
counter)
▪ A special purpose CPU status registers for storing the
current state of CPU and program under execution
▪ One ALU
▪ One local cache memory
3. The input-output (I/O) subsystem.
There is a common synchronous bus
architecture for communication between CPU, Main
Memory and I/O subsystem
 Thereis a common synchronous bus
architecture for communication between
CPU,Main Memory and I/O subsystem.
❖Example 1:VAX system(Virtual Address
eXtension) is an established line of mid-
range server computers from the Digital
Equipment Corporation (DEC). It introduced a
new operating system, VMS. VAX included a
32-bit processor and virtual memory.
 The CPU contains the master controller of the VAX
system. There are 16, 32-bit general purpose
register one of which is a Program Counter
(PC).There is also a special CPU status register
containing about the current state of the
processor being executed. The CPU contains an
ALU with an optional Floating-point accelerator,
and some local cache memory with an optional
diagnostic memory. The CPU can be intervened
by the operator through the console connected to
floppy disk.
 The CPU, the main memory( 2^32 words of 32 bit
each) and the I/O subsystem are all connected to
a common bus, the synchronous backplane
interconnection (SBI).Through this bus, all I/O
devices can communicate with each other with CPU
or with the memory. I/O devices can be connected
directly to the SBI through the unibus and its
controller or through a mass bus and its controller.
❖Example 2: mainframe IBM system 370/model
168 uniprocessor computer
 The CPU contains the instruction decoding and
execution units as well as a cache.
 Main memory is divided into four units referred
to as logical storage units (LSU), that are four way
interleaved. The storage controller provides
multiport connections between the CPU and the
four LSU’s.
 Peripherals are connected to the system via high
speed I/O channels which operate
asynchronously with the CPU.
Parallel Processing Mechanism:

 A number of parallel processing mechanisms have been

developed in uniprocessor computers. We identify them in the
following six categories:
1. Multiplicity of functional units
2. Parallelism and pipelining within the CPU
3. Overlapped CPU and I/O operations
4. Use of a hierarchical memory system
5. Balancing Of Subsystem Bandwidth
6. Multiprogramming and time sharing
1.Multiplicity of functional units

 The early computer has only one ALU in its CPU and
hence performing a long sequence of ALU instructions takes
more amount of time.
 Eg.The CDC-6600 (was the flagship of the 6000 series of
mainframe computer systems manufactured by Control
Data Corporation) has 10 functional units built into its
CPU. These 10 units are independent of each other and
may operate simultaneously. A score board is used to
keep track of the availability of the functional units and
registers being demanded. With 10 functional units and 24
registers available, the instruction issue rate can be
significantly increased.
2.Parallelism and pipelining within
the CPU :
 Parallel adders, using such techniques as carry-
look ahead and carry –save, are now built into
almost all ALUs. High speed multiplier recording
and convergence division are techniques for
exploring parallelism and the sharing of hardware
resources for the functions of multiply and Divide.
The use of multiple functional units is a form of
parallelism with the CPU.
 Various phases of instructions executions are now
pipelined, including instruction fetch, decode,
operand fetch, arithmetic logic execution, and
store result.
3. Overlapped CPU and I/O
operations :
 I/O operations can be performed simultaneously
with the CPU competitions by using separate I/O
controllers, channels, or I/O processors.
 The direct memory access (DMA) channel can be
used to provide direct information transfer
between the I/O devices and the main
memory. The DMA is conducted on a cycle stealing
basis, which is apparent to the CPU
4. Use of a hierarchical memory system :

 The CPU is 1000 times faster than memory

access. A hierarchical memory system can be used
to close up the speed gap. The hierarchical order
listed is :
 registers
 Cache
 Main Memory
 Magnetic Disk
 Magnetic Tape
 The inner most level is the register files directly
addressable by ALU.
 Cache memory can be used to serve as a buffer
between the CPU and the main memory.
 Virtual memory space can be established with
the use of disks and tapes at the outer levels.
5. Balancing Of Subsystem
Bandwidth
 CPU is the fastest unit in computer.
 The bandwidth of a system is defined as
the number of operations performed per
unit time.
 Incase of main memory the memory
bandwidth is measured by the number of
words that can be accessed per unit
time.
 Bandwidth Balancing Between CPU and
Memory:
The speed gap between the CPU and the
main memory can be closed up by using fast
cache memory between them. A block of
memory words is moved from the main
memory into the cache so that immediate
instructions can be available most of the time
from the cache.
 BandwidthBalancing Between Memory
and I/O Devices:
Input-output channels with different
speeds can be used between the slow I/O
devices and the main memory. The I/O
channels perform buffering and
multiplexing functions to transfer the data
from multiple disks into the main memory by
stealing cycles from the CPU.
6. Multiprogramming and time
sharing:
These are software approaches to achieve concurrency in a
uniprocessor system.
 Multiprogramming:
The interleaving of CPU and I/O operations among
several programs is called as Multiprogramming,ie,sharing of
many programs by the CPU
Example :
Whenever a process P1 is tied up with I/O processor for
performing input output operation at the same moment CPU can
be tied up with an process P2. This allows simultaneous
execution of programs.
 Time sharing :
Multiprogramming mainly deals with sharing of many
programs by the CPU. Sometimes high priority
programs may occupy the CPU for long time and other
programs are put up in queue. This problem can be
overcome by a concept called as Time sharing in which
every process is allotted a time slice of CPU time and
thereafter after its respective time slice is over CPU is
allotted to the next program if the process is not
completed it will be in queue waiting for the second
chance to receive the CPU time.