Instruction

Instruction is a statement by which the

operation of CPU is determined.
These instructions referred as “Machine
instructions or computer Instructions”
Elements of Machine instruction
 Operation code
 Source operand reference
 Result operand Reference
 Next instruction reference
 Instruction Sets
The collection of different instructions that
the CPU can execute is referred to as the
CPU’s instruction set.
Design Issues of Instruction Sets
 Operation repertoire
 Operand Reference
 Length of Instruction
 Data Types
 Instruction Representations
 Each instruction is represented by sequence of bits
 The instruction is divided into two fields
 Opcode field
 Operand field
 This operand field further divided into one to four
fields.
 This layout of the instruction is known as the
“Instruction Format”
 Simple instruction format

Next
Opcod Operand Operand Result
Instructio
e Address1 Address2 Address1
n
 Instruction Set Types

Instruction Set is categorized into types

based on
 Operation performed,
 number of operand addresses
 and addressing modes.
 Instruction Set category Based on
Operation

Data movement instructions: Move data

from a memory location or register to
another memory location or register
without changing its form.
 Memory
 LOAD, STORE, MOV
 I\O Instructions
 IN, OUT
 Instruction Set category Based on
Operation

Data Processing Instructions: Arithmetic

and logic (ALU) instructions - Changes the
form of one or more operands to produce a
result stored in another location
 Arithmetic
 Add, Sub, MUL
 logic Instructions
 AND, OR, ..
 Instruction Set category Based on
Operation
Control Instructions :Any instruction that
alters the normal flow of control from
executing the next instruction in sequence
 Conditional
 JNZ, JZ, JNP,JNN…..
 Un Conditional
 Jump
 4-,3-,2-,1-,and 0- address
instructions
Instruction Set categorized into four
categories based on number of operand
address in the instruction.
 4- Address Instruction
 3-Address Instruction
 2-Address Instruction
 1-Address Instruction
 0-Address Instruction
 Basic Instruction Types
9

C=A+B
How is this high-level language command
implemented in the computer?

To carry out the action

C  [A]+[B]
the contents of memory locations A and B are fetched
from memory and transferred into the processor, where
their sum is computed and then transferred to memory
location C
55:035 Computer Architecture and Organization
 Memory
24 Bits / 3 Bytes
4- Address
8
Instruction
24 24 24 24
Op ResAdd Op1Add Op2Add NextiAd
CPU Code r r r dr
Op1 Example: add M1,M2,M3, nexti
M(1)M(2)+M(3)
Op2 +
Resop

Calculation of Memory
Accesses To Execute an
To fetch Instruction
itself Opcode= Instruction
Op1Addr=1
1 Op1=1
Op2Addr=1 Op2=1
ResAddr=1 Res=1
NextiAddr=1 Total=3
Total=5

Total Memory Traffic= No. of M/A to fetch + No. of M/A to

Execute Total Memory Traffic= 5 + 3 =8
 Memory
24 Bits / 3 Bytes
3- Address
8
Instruction
24 24 24
Op ResAdd Op1Add Op2Add
CPU Code r r r
Op1 Example: add M1,M2,M3
M(1)M(2)+M(3)
Op2 +
Resop

PC 24
Calculation of Memory
Accesses To Execute an
To fetch Instruction
itself Opcode= Instruction
Op1Addr=1
1 Op1=1
Op2Addr=1 Op2=1
ResAddr=1 Res=1
Total=4 Total=3

Total Memory Traffic= No. of M/A to fetch + No. of M/A

to Execute Total Memory Traffic= 4+ 3 =7
 Memory
24 Bits / 3 Bytes
2- Address 8Instruction
24 24
Op Op1Add Op2Add
CPU Code r r
Example: add M2,M3
Op1
M(2)M(2)+M(3)
Op2 +
Resop

PC 24
Calculation of Memory
Accesses To Execute an
To fetch Instruction
itself Opcode= Instruction
Op1Addr=1
1 Op1=1
Op2Addr=1 Op2=1
Res=1
Total=3
Total=3

Total Memory Traffic= No. of M/A to fetch + No. of M/A

to Execute Total Memory Traffic= 3+ 3 =6
 Two-Address Instruction
13

An Add instruction: Add A, B performs the operation A[A]

+[B]. When the sum is calculated, the result is sent to
memory and stored in location A, replacing the original
contents of this location.
C  [A]+[B] can be implemented as
Move C, B
Add C,A

55:035 Computer Architecture and Organization

 Memory
24 Bits / 3 Bytes
1- Address 8Instruction
24
Op Op1Add
CPU Code r
Op1 Example: add M2
Op2 +
Resop
Acc

PC 24
Calculation of Memory
Accesses To Execute an
To fetch Instruction
itself Opcode= Instruction
Op1Addr=1
1 Op1=1
Total=2 Total=1

Total Memory Traffic= No. of M/A to fetch + No. of M/A

to Execute Total Memory Traffic= 2+ 1 =3
 One-Address Instruction
15

General form: Operation Source

Examples:
Add A means: Add the contents of memory location A to
the contents of the accumulator register and place the sum
back into the accumulator
Move A means: Copy the contents of memory location A
to the accumulator register
Store A means: Copy the contents of the accumulator
register to memory location A

55:035 Computer Architecture and Organization

 One-Address Instruction
16

Thus, C  [A]+[B] can be implemented as

(Assembly Language)
Move A
Add B
Store C
which means (Register Notation):
Accumulator  [A]
Accumulator  [Accumulator] + [B]
C  [Accumulator]

55:035 Computer Architecture and Organization

0-Address Instruction
3-Address
Evaluate a = (b+c)*d - e
add a, b, c ab+c 0-Address

mul a, a, d aa*d push e

sub a, a, e aa-e push d
2-Address
push c
load a, b ab
push b
add a, c aa+c add
mul a, d aa*d mul
sub a, e aa-e sub
1-Address pop a
load b Accb
add c AccAcc+c
mul d AccAcc*d
sub e AccAcc-e
store a aAcc
Write code to implement the expression: A= (B + C) * (D + E)on
3-, 2-, 1- and 0-address machines. In accordance with programming
language practice , computing the expression should not change
the values of its operands.

Ans.
3-ADDRESSMACHINE 2-ADDRESSMACHINE 1-ADDRESSMACHINE 0-ADDRESSMACHINE

Add R1, B, C Load R1, B Load B Push B

Add R2, D, E Add R1, C Add C Push C
Mul A, R1, R2 Load R2, D Store Temp Add
Add R2, E Load D Push D
Mul R2, R1 Add E Push E
Store A, R2 Mul Temp Add
Store A Mul
Pop A
 Addressing Modes
The way the operands are chosen during the program
execution is dependent on the addressing mode of the
instruction.

The term addressing modes refers to the way in which

the operand of an instruction is specified. Information
contained in the instruction code is the value of the
operand or the address of the result/operand.
 Addressing Modes

Immediate
Direct
Indirect
Register
Register Indirect
Displacement (Indexed)
Stack
 Immediate Addressing

Operand is part of instruction

Operand = address field
e.g. ADD 5
 Add 5 to contents of accumulator
 5 is operand

No memory reference to fetch data

Fast
Limited range
Immediate Addressing Diagram

Instruction

Opcode Operand
 Direct Addressing

Address field contains address of operand

Effective address (EA) = address field (A)
e.g. ADD A
 Add contents of cell A to accumulator
 Look in memory at address A for operand

Single memory reference to access data

No additional calculations to work out
effective address
 Direct Addressing Diagram

Instruction

Opcode Address A
Memory

Operand
 Indirect Addressing (1)

Memory cell pointed to by address field

contains the address of (pointer to) the
operand
EA = (A)
 Look in A, find address (A) and look there for operand
 e.g. ADD (A)
 Add contents of cell pointed to by contents of A to
accumulator
 Indirect Addressing Diagram
Instruction

Opcode Address A
Memory

Pointer to operand

Operand
 Indirect Addressing (2)

Large address space

May be nested, multilevel, cascaded
 e.g. EA = (((A)))
 Draw the diagram yourself
Multiple memory accesses to find operand
Hence slower
 Register Addressing (1)

Operand is held in register named in address

filed
EA = R
Limited number of registers
Very small address field needed
 Shorter instructions
 Faster instruction fetch
 Register Addressing (2)

No memory access

Very fast execution
Very limited address space
Multiple registers helps performance
 Requires good assembly programming or compiler
writing
 Register Addressing Diagram

Instruction

Opcode Register Address R

Registers

Operand
 Register Indirect Addressing

EA = (R)
Operand is in memory cell pointed to by
contents of register R
Large address space
One fewer memory access than indirect
addressing
 Register Indirect Addressing Diagram

Instruction

Opcode Register Address R

Memory

Registers

Pointer to Operand Operand

 Relative Addressing

A version of displacement addressing

R = Program counter, PC
EA = A + (PC)
i.e. get operand from A cells from current
location pointed to by PC
 Indexed Addressing Mode

A holds base address

R holds displacement, may be explicit or
implicit (segment registers in 8086)
Content of the index register is added to the
address part of the instruction to obtain
effective address of the operand.
EA = A + (SI)
Ex: Mov CX, [SI] 2400H
Advantage: Flexibility
Disadvantage: Complexity
 Base Register Addressing Mode

The content of the base register is added to

the address part of the instruction to obtain
the effective address of the operand.
EA = A + (BX)
Ex: Mov 2345H [BX], 0AC24H
Advantage: Flexibility
Disadvantage: Complexity
 Stack Addressing

Operand is (implicitly) on top of stack

e.g.
 ADD Pop top two items from stack
and add
 Auto Increment and Auto Decrement Addressing
Modes

This addressing mode is used when the address

stored in the register refers to a table of data in
memory, it is necessary to increment or
decrement the register after every access to the
table.
Ex: Add R1, (R2)+
R1 <- R1+R2
R2 <- R2+1
Add R1,-(R2)
R2<- R2-1
R1<- R1+R2