Module III

Technologies for building processors and memory,

Performance, Instruction set principles – Introduction,
Classifying instruction set architectures, Memory
addressing, Encoding an instruction set.
 Technologies for
building processors and memory
Electronics technology continues to evolve

• Increased capacity and performance

• Reduced cost
 Integrated Circuits(chips)-
Basics
• transistor is simply an on/off switch controlled by
electricity.
• Integrated circuit (IC) combines dozens to hundreds of
transistors into a single chip.
• VLSI- very large-scale integrated circuit -increase in
the number of transistors were from hundreds to millions.
Integrated Circuits
 Integrated Circuits(chips)
• Silica-a semiconductor device is used for manufacturing
chips
• With special chemical process, it is possible to add
materials to silicon that allow to transform into one of
three devices:
• Excellent conductors of electricity
• Excellent insulators from electricity
• Areas that can conduct or insulate under special conditions
 Integrated Circuits(chips)
• Transistors fall in the last category.
• A VLSI circuit, then, is just billions of combinations of
conductors, insulators, and switches manufactured in a
single small package.
Growth of capacity per DRAM chip
 Performance
• Performance of a system is specified in terms of Response
time & Throughput.

Response time:
• Also called execution time for the computer to complete
a task,
• Includes disk access, memory access, I/O activities,
operating system overhead, CPU execution time etc.
 Performance
• Throughput

• Also called bandwidth.

• It is the number of tasks completed per unit time.

• Ideal Case: Minimize response time and maximize

throughput
 Throughput and Response
Time
• How does following changes to a computer system affect
throughput and response time:

Case 1: Replacing the processor in a computer with a

faster version
both response time and throughput are improved.
Case 2: Adding additional processors to a system that
uses multiple processors for separate tasks
No one task gets done faster, so only throughput increases.
 Throughput and Response
Time
• We can relate performance and execution time for a
computer X:

• For two computers X and Y, if the performance of X is

greater than the performance of Y,
 Relative Performance
• If X is n times as fast as Y, then the execution time on Y is n times as
long as it is on X:

• If computer A runs a program in 10 seconds and computer B runs the

same program in 15 seconds, how much faster is A than B?
Performance ratio is=15/10=1.5

A is therefore 1.5 times as fast as B.

 Measuring Performance

• CPU execution time -also called CPU time.

• The actual time the CPU spends computing for a specific task.
• It does not include time spent waiting for I/O or running other programs.
• CPU time can be further divided into:
• user CPU time- CPU time spent in the program,
• system CPU time- CPU time spent in the operating system
performing tasks
on behalf of the program,
 Measuring Performance
• Clock time, response time, or elapsed time. These terms
mean the total time to complete a task, including disk
accesses, memory accesses, input/output (I/O) activities,
operating system overhead—everything.

• The term system performance is used to refer to elapsed

time and CPU performance to refer to user CPU time.

• All computers are constructed using a clock that determines

when events take place in the hardware. These discrete time
intervals are called clock cycles
 Measuring Performance

• Length of a clock period is referred both as the time

for a complete clock cycle (e.g., 250 picoseconds, or 250
ps)

• Clock rate/clock speed (e.g., 4 gigahertz, or 4 GHz),

which is the inverse of the clock period. It specifies no: of
clock cycles per second
 CPU Performance and Its
Factors
• CPU execution time for a program= CPU clock cycles for a program x

Clock cycle time

• Because clock rate and clock cycle time are inverses,

• Designer can improve performance by reducing the number of clock cycles

required for a program or the length of the clock cycle.
 CPU Performance and Its
Factors
Our favourite program runs in 10 seconds on computer A,
which has a 2 GHz clock. We are trying to help a computer
designer build a computer, B, which will run this program in
6 seconds. The designer has determined that a substantial
increase in the clock rate is possible, but this increase will
affect the rest of the CPU design, causing computer B to
require 1.2 times as many clock cycles as computer A for
this program. What clock rate should we tell the designer to
target?
 Example
• For system A,
Example
 Instruction Performance
• Execution time must depend on the number of instructions in a program.

• Execution time can be defined as the number of instructions executed

multiplied by the average time per instruction.

• average number of clock cycles each instruction takes to execute, is often

abbreviated as CPI.
 The Classic CPU Performance
Equation

These formulas are particularly useful because they separate the

three key factors
that affect performance.

We can use these formulas to compare two different

implementations or to evaluate a design alternative if we know its
impact on these three parameters.
Instruction Set
Principles
 Instruction Set
• The words of a computer’s language are called instructions.
• The instruction set architecture serves as the interface
between software and hardware.
• It provides the mechanism by which the software tells the
hardware what should be done.
• Software is converted to machine instructions using software
(compiler/interpreter). Then the instructions are executed
using hardware
 Instruction Set Architecture
An ISA contains :

• the functional definition of storage locations (registers,

memory)
• operations (add, multiply, branch, load, store, etc)
• precise description of how to invoke & access them
 Instruction Set
• Instruction sets work with other important parts of a
computer, such as compilers and interpreters.
• The following are three main ways instruction set
commands are used:
• Data handling and memory management.
• Arithmetic and logic operations and activities.
• Control flow activities.
 Instruction Set
• Initially designed CPU’s like Intel 4004 had less than
100’s of instructions in its instruction set.
• Today's computers have thousands of instructions.
 ISA Categorization
• The ISA of a processor can be described using following
categories:
• Operand Storage
• Operations
• Type and size of operands
• Complexity of instructions
 Classifying Instruction Set
Architectures
• Instructions execute operations that will take one or more operands.
–
• Based on where the operands are stored and whether they are named
explicitly or implicitly, the ISA can be classified as:
• Stack Architecture
• Accumulator Architecture, and
• Register-set Architecture.
• The explicit operands may be accessed directly from memory or may
need to be first loaded into temporary storage.
 Stack Architecture
• The operands are put into the stack.
• Operations take place at the top two locations on the
stack, destroying the operands, and leaving the result on
the top of the stack.
• Stack is a block of memory in RAM, but CPU keeps a stack
pointer register points to the top of the stack.
• Data in stack are first-in last out
 Stack Architecture
• Two operations, push and pop, have one operand.
• Push a value at the top of the stack, or pop the top element of
the stack to a destination.
• Other operations have implicit operands, which are the top
element(s) of the stack.
• To perform an operation, the operands are pushed into the stack
first.
• Once performed an operation, its operand(s) are deleted from the
stack, and its result is stored at the top of the stack
 Stack Architecture
• Then, it can use pop command to store the result back to the
memory.
• This architecture was used in computers in 1960s
Example: Implement the instruction C=A+B using Stack
Architecture where A, B, and C are memory addresses
Steps Involved:
PUSH A # push value at location A to the top of the stack
PUSH B # push value at location B to the top of the stack
 Stack Architecture
• ADD # add the top two elements of the
stack and save the result back to the top
of the stack

• POP C # store the value at the top of the

stack (which is the result) to location C
 Accumulator Architecture
• - It places one operand in the accumulator and one in
memory.
• The one in the accumulator is implicit, and the one in the
memory is an explicit memory address.
• The result of ALU is written back to the accumulator.
• The operand in the accumulator is loaded from memory
using the command LOAD, and the result is stored in
memory from accumulator using the command STORE
 Accumulator Architecture
Example: Implement the instruction C=A+B using Stack
Architecture where A, B, and C are memory addresses

LOAD A # load value at location A from main memory to ACC

ADD B # fetch the value at location B, add it with the value at
ACC (which is the value A), and save the result back to ACC
STORE C # store the value at ACC (which is the result of A + B)
to location C
 Accumulator Architecture
Example: Implement the instruction C=A+B
using accumulator Architecture where A, B,
and C are memory addresses

LOAD A # load value at location A from main

memory to ACC
ADD B # fetch the value at location B, add it with
the value at ACC (which is the value A), and save
the result back to ACC
STORE C # store the value at ACC (which is the
result of A + B) to location C
 Register-set Architecture
• It’s the dominant architecture used by modern computers.
• Modern CPUs have a number of general-purpose registers
(GPRs) for internal storage, at least 8 and as many as 32.
• This architecture allows fast access to temporary values,
but the instructions are longer than the accumulator
designs.
• Operations need to specify all the operands explicitly.
 Register-set Architecture
• Depending on whether the operands are available in
memory or registers, it can be further classified as
• Register-register(load-store architecture,)
• Register-memory
 Register-Register
• The registers are used for storing operands.
• It’s also called load-store architecture.
• The only instructions accessing memory are load and store
which can't perform arithmetic
• Separate load instruction is required for each source
operand in memory
• Separate store instruction is required to put a result in
memory.
 Register-Register
• Implement the instruction C=A+B using load-
store Architecture where A, B, and C are
memory addresses
• Load R1,A# load value at location A to register R1
• Load R2,B #load value at location B to register R2
• Add R3,R1,R2 #Add the values in R1 & R2 and save
the result in R3
• Store R3,C # store the value at R3 (which is the
result of A + B) to location C
 Register-memory Architecture
• In a register memory approach one of the operands may
be in memory, while the other is in a register.

• Implement the instruction C=A+B using register-

memory Architecture where A, B, and C are memory
addresses
 Register -Memory
• Load R1,A# load value at location A
to register R1
• Add R3,R1,B # fetch the value at
location B, add it with the value at R1
(which is the value A), and save the
result back to R3
• Store R3,C # store the value at R3
(which is the result of A + B) to
location C
Block diagram of different
architectures
 Instruction Set Architecture
• Most early computers used stack or accumulator-style
architectures,
• Virtually every new architecture designed after 1980 uses
a load-store register architecture.
 General Purpose Registers
2 major reasons for the emergence of general purpose registers:

1. Faster than memory.

2. More efficient for a compiler to use than other forms of internal
storage.

Disadvantages of stack
• On a stack computer the hardware must evaluate the expression in
only one order and it may have to load an operand multiple times.
 Memory Addressing
• Independent of whether the architecture is load-store or
allows any operand to be a memory reference, the
architecture must define:
• How memory addresses are interpreted and
• How they are specified.
 Memory Locations and
Addresses
• The memory consists of many millions of storage cells, each of
which can store a bit of information.
• Bit are handled in groups of fixed size.
• Memory is organized so that a group of n bits(word) can be
stored or retrieved in a single, basic operation.
• The memory of a computer can be schematically represented as a
collection of words.
• Machine instructions may require one or more words for their
representation.
 Memory Locations and
Addresses
• Modern computers have word lengths that typically range from
16 to 64 bits.
• It is impractical to assign distinct addresses to individual bit
locations in the memory.
• The most practical assignment is to have successive addresses
refer to successive byte locations in the memory.
• Byte locations have addresses 0, 1, 2, . . . .
• Thus, if the word length of the machine is 32 bits(4 bytes),
successive words are located at addresses 0, 4, 8, . . . , with each
word consisting of four bytes.
Big-Endian and Little-Endian Assignments

• There are two ways that byte addresses can be assigned

across words

• Big-endian : Most significant byte (the "big end") of the

word is placed at the byte with the lowest address.

• Little-endian: The least significant byte (the "little end")

of the word is placed at the byte with the lowest address
Big-Endian and Little-Endian Assignments
 Addressing Modes
• Microprocessor executes the instructions stored in memory
(RAM).
• It executes one instruction at a time.
• Each of the instruction contains operations and operands.
• Operation specifies the type of action to be performed.
For example: MOV, ADD, LOAD
• Operands are the data on which the operation is to be
performed.
MOV B, A:- Here MOV is operation and (B & A) are operands.
ADD B:- Here ADD is operation and (B) is operand
 Addressing Modes
• Operand can be place either in one of the processor register or in
memory.

• The different modes/methods that are used for specifying the

address of the operand in the given instructions are called the
addressing modes.

• The effective address refers to the address of an exact memory

location in which an operand’s value is actually present.
 Addressing Modes
• Addressing Modes are classified as:

• Immediate Addressing
• Direct Addressing
• Memory Indirect
• Register Direct
• Register Indirect
• Displacement
• Indexed Addressing
• Auto increment & Auto Decrement
 Immediate Addressing Mode

• The operand is specified in the instruction explicitly.

• Immediate-mode instruction consists of an operand field that
contains the actual operand.
• The immediate-mode instructions help initialize registers to a
certain constant value.
• Eg: ADD 10 - will increment the value stored in the accumulator by
10.
 Direct Addressing

• The address part of the instruction is equal to the effective

address.
• The operand would reside in memory, and the address here is
given directly by the instruction’s address field
• It is also called as absolute addressing mode.
• ADD X will increment the value stored in the
accumulator by the value stored at memory
location X.
EA=X
• AC ← AC + [X]
 Memory Indirect

• The address field of the instruction specifies the address of

memory location that contains the effective address of the
operand.
• Two references to memory are required to fetch the
operand.
• ADD (X ) will increment the value stored in the accumulator
by the value stored at memory location specified by X.
EA=( X)
• AC ← AC + [[X]]
 Register Direct/Register
• The operand is contained in a register set.
• The address field of the instruction refers to a CPU register that
contains the operand.
• No reference to memory is required to fetch the operand.
• ADD R will increment the value stored in the accumulator by the
content of register R.
EA=R
• AC ← AC + [R]
• This addressing mode is similar to
direct addressing mode.
 Register Indirect
• The address field of the instruction refers to a CPU
register that contains the effective address of the operand.
• Only one reference to memory is required to fetch the
operand.
• ADD (R ) will increment the value stored in the
accumulator by the content of memory location specified
in register R.
• EA=( R )
• AC ← AC + [[R]]
 Displacement
• Combines capabilities of direct addressing & register
indirect addressing
EA=A+(R)
• address field holds two values
• The value contained in Address Field A is used directly
• The other address field refers to a register (R ) whose
contents are added to A to produce the
effective address.
 Indexed Addressing
• In index addressing mode, contents of Index register is added
to address part of instruction to obtain effective address.

• The address part of instruction holds the beginning/base

address and is called as base.

• The index register hold the index value, which is +ve

• Base remains same, the index changes.

 Indexed Addressing
• When the base is added to the index register the resultant number is
the memory location where the operand will be placed.

• Effective Address
= Content of Index Register + Address part of the
instruction.

• The index addressing mode is pretty helpful whenever the instructions

in a program access an array or large ranges of memory addresses.
Indexed Addressing
 Auto-Increment Addressing Mode

• special case of Register Indirect Addressing Mode where

Effective Address of the Operand = Content of Register

• After accessing the operand, the content of the register is

automatically incremented by step size ‘d’- size of operand
accessed.
• Only one reference to memory is required to fetch the operand.
• Symbolically it is represented as below: (R)+
• example: ADD (R2)+, R
 Auto-Decrement Addressing Mode

• Special case of Register Indirect Addressing Mode where-

Effective Address of the Operand = Content of Register –
Step Size.

• In this mode, first the Register value is decremented and then

operand value is fetched from the memory.

• Symbolically it is presented as -(R)

example: ADD -(R2),R0
 Encoding an Instruction Set
• Instructions are encoded into a binary representation for
execution by the processor.
• The operation is typically specified in one field, called the
opcode.
• The important decision is how to encode the addressing
modes with the operations.
• This decision depends on the range of addressing modes
and the degree of independence between opcodes and
modes.
 Encoding an Instruction Set
• Some older computers have one to five operands with 10 addressing
modes for each operand.
• For such a large number of combinations, typically a separate address
specifier is needed for each operand:
• The address specifier tells what addressing mode is used to access the
operand.
• At the other extreme are load-store computers with only one memory
operand and only one or two addressing modes;
• In this case, the addressing mode can be encoded as part of the opcode.
 Encoding an Instruction Set

• While encoding the instructions, the number of registers

and the number of addressing modes both have a
significant impact on the size of instructions.

• For most instructions many more bits are consumed in

encoding addressing modes and register fields than in
specifying the opcode.
 Encoding an Instruction Set

• The architect must balance several competing forces when

encoding the instruction set:
1. The desire to have as many registers and addressing
modes as possible.
2. The impact of the size of the register and addressing mode
fields on the average instruction size and hence on the
average program size.
3. A desire to have instructions encoded into lengths that will
be easy to handle in a pipelined implementation.
 Encoding an Instruction Set
• Instruction set format defines the layout of bits allocated
to various elements of an instruction.
• Three popular formats used for encoding the instruction
set are:
• Variable
• Fixed
• Hybrid
Encoding an Instruction Set
 Encoding an Instruction Set-
Variable
• Uses different numbers of bits to encode the instructions in the
instruction set architecture.
• Instruction length depends on the number of inputs to the
instruction, the addressing modes used, and other factors.
• The variable format can support any number of operands.
• Suitable when multiple type of addressing modes and variation
in the number of operands are needed in a machine instruction
Encoding an Instruction Set-
Variable
• Advantages: Program length in memory is less when a
limited number of operands are used in most instructions

• Disadvantages: greatly increases the complexity of the

logic required to decode instructions, since parts of the
instruction, such as the input operands, may be stored in
different bit positions in different instruction
 Encoding an Instruction Set-
Fixed Length
• Uses the same number of bits to encode each instruction.
• Used by modern 32-bit processors, without memory
constraints.
• Best when there are few addressing modes and operations
• Fixed format always has the same number of operands,
with the addressing modes (if options exist) specified as
part of the opcode.
 Encoding an Instruction Set-
Fixed Length
• Generally results in the largest code size.

• Advantages: Simple to decode

• Disadvantage: Program length in memory is fixed even if
limited number of operands are used in most instructions
 Encoding an Instruction Set-
Hybrid
• Introduced to reduce the variability in size and complexity
of the variable format but provide multiple instruction
lengths to reduce code size.

• The hybrid approach has multiple formats specified by the

opcode, adding one or two fields to specify the addressing
mode and one or two fields to specify the operand
address.