Unit-2

ARM Assembly Programming

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Load-Store Architecture

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 ARM instruction set
• data processing instructions
• branch instructions
• load-store instructions
• software interrupt instruction
• program status register instructions.

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 Data Processing Instructions
• The data processing instructions manipulate
data within registers.
• Most data processing instructions can process
one of their operands using the barrel shifter.
• If you use the S suffix on a data processing
instruction, then it updates the flags in the
cpsr.

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 Data Processing Instructions
• move instructions
• arithmetic instructions
• logical instructions
• comparison instructions
• Multiply instructions.

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Move Instructions

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Barrel shifter with MOV

logical shift left (LSL)

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 Arithmetic Instructions
• The arithmetic instructions implement
addition and subtraction of 32-bit signed and
unsigned values.

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Using the Barrel Shifter with Arithmetic
Instructions

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Logical Instructions

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 Logical Instructions
• BIC instruction is particularly useful when
clearing status bits and is frequently used to
change interrupt masks in the cpsr.
• The logical instructions update the cpsr flags
only if the S suffix is present.
• These instructions can use barrel-shifted
second operands in the same way as the
arithmetic instructions.

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 Comparison Instructions

• The comparison instructions are used to

compare or test a register with a 32-bit value.
• They update the cpsr flag bits according to the
result, but do not affect other registers.
• After the bits have been set, the information
can then be used to change program flow by
using conditional execution.
• You do not need to apply the S suffix for
comparison instructions to update the flags.
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N is the result of the shifter operation.

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 Comparison Instructions

• The CMP is effectively a subtract instruction

with the result discarded
• similarly the TST instruction is a logical AND
operation, and TEQ is a logical exclusive OR
operation.
• For each, the results are discarded but the
condition bits are updated in the cpsr. It is
important to understand that comparison
instructions only modify the condition flags of
the cpsr and do not affect the registers being
compared. 33
Multiply Instructions

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 Multiply Instructions
• The long multiply instructions (SMLAL, SMULL,
UMLAL, and UMULL) produce a 64-bit result.
• The result is too large to fit a single 32-bit
register so the result is placed in two registers
labeled RdLo and RdHi.
• RdLo holds the lower 32 bits of the 64-bit
result, and RdHi holds the higher 32 bits of the
64-bit result

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 Branch Instructions

• A branch instruction changes the flow of

execution or is used to call a routine.
• This type of instruction allows programs to
have subroutines, if-then-else structures, and
loops.
• The change of execution flow forces the
program counter pc to point to a new address.
• The ARMv5E instruction set includes four
different branch instructions

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 Branch Instructions
• Branches are used to change execution flow.
• Most assemblers hide the details of a branch
instruction encoding by using labels.
• In previous example, forward and backward are
the labels.
• The branch labels are placed at the beginning
of the line and are used to mark an address
that can be used later by the assembler to
calculate the branch offset.
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 Branch Instructions

• The branch exchange (BX) and branch exchange with

link (BLX) are the third type of branch instruction.
• The BX instruction uses an absolute address stored
in register Rm.
• It is primarily used to branch to and from Thumb
code.
• The T bit in the cpsr is updated by the least
significant bit of the branch register.
• Similarly the BLX instruction updates the T bit of the
cpsr with the least significant bit and additionally
sets the link register with the return address.
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 Load-Store Instructions
• Load-store instructions transfer data between
memory and processor registers.
• There are three types of load-store
instructions: single-register transfer, multiple-
register transfer, and swap.

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 Single-Register Transfer

• These instructions are used for moving a

single data item in and out of a register.
• The data types supported are signed and
unsigned words (32-bit), half words (16-bit),
and bytes.

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 Single-Register Load-Store Addressing Modes

• The ARM instruction set provides different

modes for addressing memory.
• These modes incorporate one of the indexing
methods: pre index with write back, pre index,
and post index.

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• The preindex mode is useful for accessing an element in a
data structure.
• The postindex and preindex with writeback modes are useful
for traversing an array.
• A signed offset or register is denoted by “+/−”, identifying that
it is either a positive or negative offset from the base address
register Rn.

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 Multiple-Register Transfer
• Load-store multiple instructions can transfer
multiple registers between memory and the
processor in a single instruction.
• The transfer occurs from a base address
register Rn pointing into memory.
• Multiple-register transfer instructions are
more efficient from single-register transfers
for moving blocks of data around memory and
saving and restoring context and stacks.
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Multiple-Register Transfer

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 Stack Operations

• The ARM architecture uses the load-store

multiple instructions to carry out stack
operations.
• The pop operation (removing data from a
stack) uses a load multiple instruction;
• similarly, the push operation (placing data onto
the stack) uses a store multiple instruction.
• stack is either ascending (A) or descending (D).
Ascending stacks grow towards higher
memory addresses; in contrast, descending
stacks grow towards lower memory addresses. 59
 Stack Operations

• When you use a full stack (F), the stack pointer

sp points to an address that is the last used or
full location (i.e., sp points to the last item on
the stack).
• In contrast, if you use an empty stack (E) the
sp points to an address that is the first unused
or empty location
• There are a number of load-store multiple
addressing mode aliases available to support
stack operations
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 Stack Operations

• Next to the pop column is the actual load multiple

instruction equivalent. For example, a full ascending
stack would have the notation FA appended to the
load multiple instruction—LDMFA. This would be
translated into an LDMDA instruction.
• ARMhas specified an ARM-Thumb Procedure Call
Standard (ATPCS) that defines how routines are
called and how registers are allocated.
• In the ATPCS, stacks are defined as being full
descending stacks. Thus, the LDMFD and STMFD
instructions provide the pop and push functions,
respectively.
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 Stack Operations

• When handling a checked stack there are three

attributes that need to be preserved: the stack base,
the stack pointer, and the stack limit.
• The stack base is the starting address of the stack in
memory.
• The stack pointer initially points to the stack base; as
data is pushed onto the stack, the stack pointer
descends memory and continuously points to the top
of stack.
• If the stack pointer passes the stack limit, then a stack
overflow error has occurred.
• If the stack pointer goes back past the stack base, then
a stack underflow error has occurred. 65
 Swap Instruction
• The swap instruction is a special case of a load-
store instruction.
• It swaps the contents of memory with the
contents of a register.
• This instruction is an atomic operation—it reads
and writes a location in the same bus operation,
preventing any other instruction from reading or
writing to that location until it completes.
• Swap cannot be interrupted by any other
instruction or any other bus access. We say the
system “holds the bus” until the transaction is
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The swap instruction loads a word from memory into register r0 and
overwrites the memory with register r1.

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 Software Interrupt Instruction
• A software interrupt instruction (SWI) causes a
software interrupt exception, which provides a
mechanism for applications to call operating
system routines.

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 Software Interrupt Instruction
• When the processor executes an SWI
instruction, it sets the program counter pc to
the offset 0x8 in the vector table.
• The instruction also forces the processor mode
to SVC, which allows an operating system
routine to be called in a privileged mode.
• Each SWI instruction has an associated SWI
number, which is used to represent a particular
function call or feature.
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 Program Status Register Instructions

• The ARM instruction set provides two

instructions to directly control a program
status register (psr).
• The MRS instruction transfers the contents of
either the cpsr or spsr into a register; in the
reverse direction
• the MSR instruction transfers the contents of a
register into the cpsr or spsr.
• Together these instructions are used to read
and write the cpsr and spsr.
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In the syntax you can see a label called fields. This can be any combination of
control (c), extension (x), status (s), and flags (f )

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 Coprocessor Instructions

• Coprocessor instructions are used to extend the

instruction set.
• A coprocessor can either provide additional
computation capability or be used to control the
memory subsystem including caches and memory
management.
• The coprocessor instructions include data processing,
register transfer, and memory transfer instructions

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 Loading Constants
• To aid programming there are two
pseudoinstructions to move a 32-bit value into
a register.

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Arm thumb instruction

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Assembler directives

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 ASEMBLY PROGRAMMING
• REFER LAB PROGRAMS

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