Module 2

Introduction to the ARM Instruction

Set
 ARM instructions classified as—
Data processing instructions
Branch instructions
Load-store instructions
Software interrupt instruction
Program status register instructions.
 1. Data Processing Instructions

Move instructions
Arithmetic instructions
Logical instructions
Comparison instructions
Multiply instructions

Most data processing instructions can process one of their operands

using the barrel shifter. If you use the S suffix on a data processing
instruction, then it updates the flags in the cpsr. Move and logical
operations update the carry flag C, negative flag N, and zero flag Z. o
The C flag is set from the result of the barrel shift as the last bit
shifted out. o The N flag is set to bit 31 of the result. o The Z flag is set
if the result is zero
 MOVe Instructions:
Move instruction copies N into a destination register Rd, where N
is a register or immediate value. This instruction is useful for
setting initial values and transferring data between registers.

Example:
The MOV instruction takes the contents of register r5 and copies
them into register r7, in this case, taking the value 5, and
overwriting the value 8 in register r7. PRE r5 = 5 r7 = 8 MOV r7,
r5 ; let r7 = r5 POST r5 = 5 r7 = 5
Barrel Shifter: In above Example, we showed a MOV instruction where
N is a simple register. But N can be more than just a register or
immediate value; it can also be a register Rm that has been
preprocessed by the barrel shifter prior to being used by a data
processing instruction.
Data processing instructions are processed within the arithmetic logic
unit (ALU).
A unique and powerful feature of the ARM processor is the ability to
shift the 32-bit binary pattern in one of the source registers left or right
by a specific number of positions before it enters the ALU.
Pre-processing or shift occurs within the cycle time of the instruction.
This shift increases the power and flexibility of many data processing
operations.
This is particularly useful for loading constants into a register and
achieving fast multiplies or division by a power of 2.
There are data processing instructions that do not use the barrel shift,
for example, the MUL (multiply), CLZ (count leading zeros), and QADD
(signed saturated 32-bit add) instructions
Figure shows the data flow between the ALU and the barrel shifter. 
Register Rn enters the ALU without any pre- processing of registers. 
We apply a logical shift left (LSL) to register Rm before moving it to the
destination register. This is the same as applying the standard C
language shift operator « to the register.
This is equivalent to – Rd = Rn AND NOT (N) In this example, register r2 contains a binary
pattern where every binary 1 in r2 clears a corresponding bit location in register r1. This
instruction is particularly useful when clearing status bits and is frequently used to
change interrupt masks in the cpsr. NOTE: The logical instructions update the cpsr flags
only if the S suffix is present. These instructions can use barrel-shifted second operands in
the same way as the arithmetic instruction
Comparison Instructions:
The comparison instructions are used to compare or test a register with a 32-bit value. 
They update the cpsr flag bits according to the result, but do not affect other registers.
After the bits have been set, the information can then be used to change program flow by
using conditional execution.
It is not required to apply the S suffix for comparison instructions to update the flag
Example: This example shows a CMP comparison instruction. You can see that both
registers, r0 and r9, are equal before executing the instruction.
The value of the Z flag prior to execution is 0 and is represented by a lowercase z.
After execution the Z flag changes to 1 or an uppercase Z.
This change indicates equality.
PRE cpsr = nzcvqiFt
_USER r0 = 4 r9 = 4 CMP r0, r9
POST cpsr = nZcvqiFt_USE
The CMP is effectively a subtract instruction with the result discarded; similarly the TST
instruction is a logical AND operation, and TEQ is a logical exclusive OR operation.  For
each, the results are discarded but the condition bits are updated in the cpsr.  It is
important to understand that comparison instructions only modify the condition flags of
the cpsr and do not affect the registers being compared
Multiply Instructions:

The multiply instructions multiply the contents of a pair of registers and, depending upon
the instruction, accumulate the results in with another register.
The long multiplies accumulate onto a pair of registers representing a 64-bit value.
The final result is placed in a destination register or a pair of registers.
Example:
This example shows a simple multiply instruction that multiplies registers r1 and r2
together and places the result into register r0. In this example, register r1 is equal to the
value 2, and r2 is equal to 2. The result, 4, is then placed into register r0.
 PRE r0 = 0x00000000
r1 = 0x00000002
r2 = 0x00000002
MUL r0, r1, r2 ; r0 = r1*r2
POST
r0 = 0x00000004
r1 = 0x00000002
r2 = 0x00000002
Example: The instruction multiplies registers r2 and r3 and places the result into
register r0 and r1.
Register r0 contains the lower 32 bits, and register r1 contains the higher 32 bits of
the 64-bit result.
PRE r0 = 0x00000000
r1 = 0x00000000
r2 = 0xf0000002
r3 = 0x00000002
UMULL r0, r1, r2, r3 ;
[r1,r0] = r2*r3
POST r0 = 0xe0000004 ; = RdLo
r1 = 0x00000001 ; = RdHi
BRANCH INSTRUCTIONS:
A branch instruction changes the flow of execution or is used to call a routine. This type
of instruction allows programs to have subroutines, if-then-else structures, and loops.
The change of execution flow forces the program counter pc to point to a new address.
The ARMv5E instruction set includes four different branch instructions
code 32 @ ARM mode
add r2, pc, #1 ; put PC+1 into R2
bx r2; branch + exchange to R2
Branch to target address, change instruction set
The BX instruction branches to the address contained in a specified register.
The value of bit 0 of the branch address determines whether execution continues in ARM
state or Thumb state.
This example shows a forward and backward branch. Because these loops are address
specific, we do not include the pre- and post-conditions. The forward branch skips three
instructions. The backward branch creates an infinite loop.

B forward
ADD r1, r2, #4
ADD r0, r6, #2
ADD r3, r7, #4
Forward
SUB r1, r2, #4 ---------------------------------------------------
backward
ADD r1, r2, #4
SUB r1, r2, #4
ADD r4, r6, r7
B backward
In this example, forward and backward are the labels.
The branch labels are placed at the beginning of the line and are used to mark an
address that can be used later by the assembler to calculate the branch offset.
The branch with link, or BL, instruction is similar to the B instruction but overwrites the
link register lr with a return address.
It performs a subroutine call.
Example: This example shows a simple fragment of code that, branches to a subroutine
using the BL instruction.
To return from a subroutine, you copy the link register to the pc. BL subroutine ; branch
to subroutine
CMP r1, #5 ; compare r1 with 5
MOVEQ r1, #0 ; if (r1==5) then r1 = 0 :
subroutine
MOV pc, lr ; return by moving pc = l
overwrites the link register lr with a return address. It performs a subroutine
call.
Example: This example shows a simple fragment of code that, branches to a
subroutine using tthe BL instruction.
To return from a subroutine, you copy the link register to the pc.
BL subroutine ; branch to subroutine
CMP r1, #5 ; compare r1 with 5
MOVEQ r1, #0 ;
if (r1==5) then r1 = 0
:
subroutine
MOV pc, lr ; return by moving pc = lr
The branch exchange (BX) and branch exchange with link (BLX) are the third
type of branch instruction
The BX instruction uses an absolute address stored in register Rm. It is
primarily used to branch to and from Thumb code.
The T bit in the cpsr is updated by the least significant bit of the branch
register.
Similarly the BLX instruction updates the T bit of the cpsr with the least
significant bit and additionally sets the link register with the return address
The branch exchange (BX) and branch exchange with link (BLX) are the third type of
branch instruction.
The BX instruction uses an absolute address stored in register Rm. It is primarily used
to branch to and from Thumb code.
The T bit in the cpsr is updated by the least significant bit of the branch register.
Similarly the BLX instruction updates the T bit of the cpsr with the least significant bit
and additionally sets the link register with the return address
LOAD-STORE INSTRUCTIONS:
Load-store instructions transfer data between memory and processor registers.
There are three types of load-store instructions: single-register transfer, multiple-
register transfer, and swap.
Single-Register Transfer: These instructions are used for moving a single data item in
and out of a register.
The data types supported are signed and unsigned words (32-bit), half-words (16-bit),
and bytes.
LDR and STR instructions can load and store data on a boundary alignment that is the
same as the data type size being loaded or stored.
For example, LDR can only load 32-bit words on a memory address that is a multiple of
four bytes—0, 4, 8, and so on.
Example: This example shows a load from a memory address contained in register r1,
followed by a store back to the same address in memory
;;
load register r0 with the contents of ; the memory address pointed to by register ; r1. ;
LDR r0, [r1] ; = LDR r0,
[r1, #0] ; ; store the contents of register r0 to ; the memory address pointed to by ;
register r1. ;
STR r0, [r1] ; = STR r0, [r1, #0]
The first instruction loads a word from the address stored in register r1 and places it into
register r0.
The second instruction goes the other way by storing the contents of register r0 to the
address contained in register r1.
The offset from register r1 is zero. Register r1 is called the base address register.
Software Interrupt Instructions

A software interrupt instruction (SWI) causes a software interrupt exception, which

provides a mechanism for applications to call operating system routines. When the
processor executes an SWI instruction, it sets the program counter pc to the offset
0x8 in the vector table.
The instruction also forces the processor mode to SVC, which allows an operating
system routine to be called in a privileged mode. Each SWI instruction has an
associated SWI number, which is used to represent a particular function call or
feature
simple example of an SWI call with SWI number 0x123456, used by ARM toolkits as
a debugging SWI.
Typically the SWI instruction is executed in user mode.
PRE cpsr = nzcVqift_USER
pc = 0x00008000
lr = 0x003fffff ;
lr = r14 r0 = 0x12 0x00008000
SWI 0x123456 passed back via register
POST
cpsr = nzcVqIft_SVC
spsr = nzcVqift_USER
pc = 0x00000008
lr = 0x00008004
r0 = 0x12
Since SWI instructions are used to call operating system routines, you need some
form of parameter passing.
This is achieved using registers. In this example, register r0 is used to pass the
parameter 0x12. The return values are also back via registers

Code called the SWI handler is required to process the SWI call.
The handler obtains the SWI number using the address of the executed instruction,
which is calculated from the link register lr.
The SWI number is determined by
SWI_Number = AND NOT (0xff000000)
Here the SWI instruction is the actual 32-bit SWI instruction executed by the
processor
The following Table shows the different addressing modes for the load-store multiple
instructions. Here N is the number of registers in the list of registers. Table: Addressing
Mode for Load-Store Multiple Instructions