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8086 Interrupts

The document provides an overview of interrupt control in the 8086 microprocessor, detailing the types of interrupts, including hardware and non-maskable interrupts, and their associated signals. It explains the interrupt service routine process, the role of the 8259 Programmable Interrupt Controller, and the differences between hardware interrupts and software interrupts. Additionally, it covers predefined interrupts, masking, prioritization, and the importance of the interrupt vector table.

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12 views43 pages

8086 Interrupts

The document provides an overview of interrupt control in the 8086 microprocessor, detailing the types of interrupts, including hardware and non-maskable interrupts, and their associated signals. It explains the interrupt service routine process, the role of the 8259 Programmable Interrupt Controller, and the differences between hardware interrupts and software interrupts. Additionally, it covers predefined interrupts, masking, prioritization, and the importance of the interrupt vector table.

Uploaded by

Sathvik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Interrupt Control

8086
Pins and Signals
Microprocessor
Common signals

AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are


multiplexed with data.

When AD lines are used to transmit


memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines


the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are


multiplexed with status signals

2
General flow
Process in
execution

Returns
Main Process requires I/O service
Program

I/O
Interrupt

Interrupt
Service
Routine
Flowchart of basic interrupt
mechanism
Fetch
Instruction

Increment PC
Decode and
Execute instr.

No
Int request line
Restore PC
active

Yes
Interrupt
Store PC service
Routine
What is Interrupt
8086/88 Interrupts

• 256 Interrupts.

• Types 00 ……. FF.

• Type is provided in a specified timing.


Hardware Interrupts

• The 8086/8088 have three pins


associated with hardware interrupts
– NMI (nonmaskable interrupt – input)
– INTR (interrupt request - input)
– INTA* (interrupt acknowledge –
output)
Non-maskable Interrupts

• This interrupt is triggered on a high signal on


the NMI pin.
– CPU finishes current instruction
– INT 02 is automatically called
• It is not maskable – that is, it can not be
disabled by software.
• It is useful in small scale projects, and for
emergency operations (memory parity
checks)
Non-maskable Interrupts

• It is possible to mask an NMI via a


hardware/software solution
– Use a single bit output port on an 8255 PPI
– Use an AND gate to combine this signal with the original
NMI signal

From PPI
NMI CPU
Device
Interrupt
Request
Hardware Interrupts

• After executing each instruction, the CPU


checks the input signal on the INTR pin
– If high, then a device has requested an
interrupt
• The CPU acknowledges the interrupt by
activating INTA*
• The external device must provide the type on
the data bus (00 – FFh)
Hardware Interrupts

• These interrupts can be masked by


changing the status of the interrupt
flag
– STI sets the interrupt flag (IF) and
thus allows interrupts
– CLI clears the IF and blocks
hardware interrupts
Hardware Interrupts

• A special integrated circuit is available to


prioritize interrupts and provide their type
– 8259 Programmable Interrupt Controller
(PIC)
– Like the other programmable ICs we’ve
seen, you must initially program the 8259
via software instructions from the CPU
Hardware Interrupts

D0-7
IR0
INTR
8086/ 8259
8088 INTA* PIC
NMI IR7
AD0-AD7
D0 –D7 IR0 IR0
INTR INT
INTA INTA

8259
RD RD IR7 IR7
WR WR CAS0
CAS1
A0 CAS2
CS SP/EN +5v
4.7kohm
INT INTA

Data Control Logic


Bus

IR0
In- Interrupt
service Priority Request
Register Resolver Register
(ISR)
(IRR)
IR7

Interrupt mask register


IR0 INT0
INT1
INT2
8259 INT3
INT4
R1
INT5
+5v SP/EN
IR7
470ohm 0 1 2 INT6

0 1 2
IR0 INT7
INT

8259

SP/EN IR7 INT14


Part
Part of
of a
a
maximum
maximum
Mode
Mode
system
system

PC/XT Hardware
Interrupts
PC AT Hardware
Interrupts
Interrupt Vector Table
Answering an Interrupt

• Save status
– FR, IP, CS

• Service the interrupt


– Interrupt service routing (ISR) or Interrupt handler
– Based on Interrupt vector number
– From Interrupt vector table
– Four bytes for every interrupt: CS:IP

• Return to original position by IRET


Difference with Call

1. CALL FAR can jump to any location (1M


range)
2. Hardware interrupts can come at any time.
3. Interrupts are maskable.
4. After CALL only CS:IP is saved
5. End of routine: RETF vs. IRET.
Interrupt Categories

• Hardware interrupts:
– Only 3 pin, but how 256 interrupt?
– INTR (in), NMI (in), and INTA (out)
– INTR can be masked by CLI / STI
– Active high.
» 80x86 finished instruction.
» Push FR, CS, IP
– NMI: INT 02.
• Software interrupts
– INT nn
– Example: INT 21H (DOS functions)
Interrupt and Flags
Predefined Interrupts

• INT 00 (divide error)


• INT 01 (single step)
– Set Trap flag (how?)
– PUSHF, POP AX, …
– Trace in debug
• INT 02 (NMI)
• INT 03 (breakpoint)
• INT 04 (signed number overflow)
– INT) instruction
» Examine Interrupt vector table.
» Examine INT 12H (size of conventional RAM in AX)
8259
Control Word (initialization)
ICW1, ICW2
ICW3, ICW4
Example
Masking and Prioritization

• OCW (operation command word)


Programming OCWs
OCW3
8259 in PC XT

ICW1: 13H
ICW2: 08H
ICW3: 09H
Interrupt Sources in PC
Sources of NMI
8259s in AT
IRQ9 Instead of IRQ2
Interrupts (Summary)
Edge Triggered and Interrupt
Sharing

• Level triggered mode: IRQ line should be


brought down before EOI.
• Edge triggered mode: noise on IRQ lines
might cause false interrupts.

• New computer and busses.


– Level triggered.
– Interrupt sharing.

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