Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

The Inverter
July 30, 2002

© Digital Integrated Circuits2nd Inverter

 The CMOS Inverter: A First Glance
V DD

V in V out

CL

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CMOS Inverter
N Well VDD

VDD PMOS 2

Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS

NMOS
GND

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 Two Inverters
Share power and ground

Abut cells

VDD
Connect in Metal

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 CMOS Inverter
First-Order DC Analysis
V DD V DD

Rp
VOL = 0
VOH = VDD
V out VM = f(Rn, Rp)
V out

Rn

V in 5 V DD V in 5 0

© Digital Integrated Circuits2nd Inverter

 CMOS Inverter: Transient Response
V DD V DD

Rp tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout
CL CL
Rn

Vin 5 0 Vin 5 V DD
(a) Low-to-high (b) High-to-low

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 Voltage Transfer
Characteristic

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PMOS Load Lines

IDn
V in = VDD +VGSp
IDn = - IDp
V out = VDD +VDSp

Vout

IDp IDn IDn

Vin=0 Vin=0

Vin=1.5 Vin=1.5

V DSp VDSp Vout

VGSp=-1

VGSp=-2.5
Vin = V DD+VGSp Vout = V DD+VDSp
IDn = - IDp

© Digital Integrated Circuits2nd Inverter

CMOS Inverter Load Characteristics

ID n
Vin = 0 Vin = 2.5

PMOS Vin = 0.5 Vin = 2 NMOS

Vin = 1 Vin = 1.5

Vin = 1.5 Vin = 1
Vin = 1.5 Vin = 1
Vin = 2 Vin = 0.5

Vin = 2.5 Vin = 0

Vout

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CMOS Inverter VTC

Vout NMOS off

2.5 PMOS res
NMOS s at
PMOS res
2

NMOS sat
1.5

PMOS sat
1

NMOS res
PMOS sat NMOS res
0.5

PMOS off

0.5 1 1.5 2 2 .5 Vin

© Digital Integrated Circuits2nd Inverter
 Switching Threshold as a function
of Transistor Ratio
1.8

1.7

1.6

1.5

1.4
V (V)

1.3
M

1.2

1.1

0.9

0.8
0 1
10 10
W /W
p n
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© Digital Integrated Circuits2nd Inverter
 Determining VIH and VIL
Vout

V OH

VM

V in
V OL
V IL V IH

A simplified approach

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 Inverter Gain
0

-2

-4

-6

-8
gain

-10

-12

-14

-16

-18
0 0.5 1 1.5 2 2.5
Vin (V)

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 Gain as a function of VDD
2.5 0.2

2
0.15

1.5

V out (V)
V out (V)

0.1

0.05
0.5
Gain=-1
0
0 0 0.05 0.1 0.15 0.2
0 0.5 1 1.5 2 2.5 Vin (V)
Vin (V)

© Digital Integrated Circuits2nd Inverter

Simulated VTC
2.5

1.5
Vout (V)

0.5

0
0 0.5 1 1.5 2 2.5
Vin (V)

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 Impact of Process Variations
2.5

2
Good PMOS
Bad NMOS
1.5
Vout(V)

Nominal

1
Good NMOS
Bad PMOS

0.5

0
0 0.5 1 1.5 2 2.5
Vin (V)

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 Propagation Delay

© Digital Integrated Circuits2nd Inverter

 CMOS Inverter Propagation Delay
Approach 1
VDD

tpHL = C L Vswing/2
Iav

Vout CL
~
Iav CL kn VDD

Vin = V DD

© Digital Integrated Circuits2nd Inverter

 CMOS Inverter Propagation Delay
Approach 2
VDD

tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout ln(0.5)
CL
1 VDD
Ron

0.5
0.36

Vin = V DD
t
RonCL

© Digital Integrated Circuits2nd Inverter

CMOS Inverters
VDD

PMOS

1.2m
=2
Out
In
Metal1

Polysilicon

NMOS
GND

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 Transient Response
3

2.5
?
2
tp = 0.69 CL
1.5
(Reqn+Reqp)/2
Vout(V)

1 tpLH tpHL

0.5

-0.5
0 0.5 1 1.5 2 2.5
t (sec) -10
x 10

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© Digital Integrated Circuits2nd Inverter
 Design for Performance
 Keep capacitances small
 Increase transistor sizes
 watch out for self-loading!
 Increase VDD (????)

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Delay as a function of VDD

5.5

4.5

4
tp(normalized)

3.5

2.5

1.5

1
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
VDD(V)

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 NMOS/PMOS ratio  = Wp/Wn
-11
x 10
5

tpLH tpHL
4.5

tp
tp(sec)

3.5

3
1 1.5 2 2.5 3 3.5 4 4.5 5


© Digital Integrated Circuits2nd Inverter

 Device Sizing
-11
x 10
3.8

3.6 (for fixed load)

3.4

3.2

3
t p (sec)

2.8

2.6

2.4
Self-loading effect:
2.2 Intrinsic capacitances
2
dominate
2 4 6 8 10 12 14
S

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Impact of Rise Time on Delay
0.35

0.3
tpHL(nsec)

0.25

0.2

0.15
0 0.2 0.4 0.6 0.8 1
trise (nsec)

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© Digital Integrated Circuits2nd Inverter
© Digital Integrated Circuits2nd Inverter
© Digital Integrated Circuits2nd Inverter
© Digital Integrated Circuits2nd Inverter
 Inverter Sizing

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 Inverter Chain

In Out

CL

If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?

May need some additional constraints.

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 Inverter Delay
• Minimum length devices, L=0.25m
• Assume that for WP = 2WN =2W 2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays W
• Analyze as an RC network
1 1
 WP   WN 
RP Runit   Runit   RN RW
 Wunit   Wunit 
Delay (D): tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL
W
Load for the next stage: C gin 3 Cunit
Wunit
© Digital Integrated Circuits2nd Inverter
 Inverter with Load
Delay

RW

CL
RW Load (CL)
tp = k RWCL

k is a constant, equal to 0.69

Assumptions: no load -> zero delay
Wunit = 1
© Digital Integrated Circuits2nd Inverter
 Inverter with Load
CP = 2Cunit Delay

2W

W
Cint CL

Load
CN = Cunit

Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)

= Delay (Internal) + Delay (Load)

© Digital Integrated Circuits2nd Inverter

 Delay Formula

Delay ~ RW Cint  C L 

t p kRW Cint 1  C L / Cint  t p 0 1  f /  

Cint = Cgin with   1

f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
© Digital Integrated Circuits2nd Inverter
 Apply to Inverter Chain

In Out

1 2 N CL

tp = tp1 + tp2 + …+ tpN

 C gin, j 1 
t pj ~ Runit Cunit  1  
 C 
 gin , j 
N N  C gin, j 1 
t p  t p , j t p 0   1   , C gin, N 1 C L
 C
i 1 

j 1 gin , j 

© Digital Integrated Circuits2nd Inverter

 Optimal Tapering for Given N

Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N

Minimize the delay, find N - 1 partial derivatives

Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1

Size of each stage is the geometric mean of two neighbors

C gin , j  C gin , j  1C gin , j 1

- each stage has the same effective fanout (Cout/Cin)

- each stage has the same delay

© Digital Integrated Circuits2nd Inverter

 Optimum Delay and Number of
Stages
When each stage is sized by f and has same eff. fanout f:
N
f F C L / C gin,1

Effective fanout of each stage:

f N F
Minimum path delay


t p  Nt p 0 1  N F /  
© Digital Integrated Circuits2nd Inverter
 Example

In Out

1 f f2 CL= 8 C1
C1

CL/C1 has to be evenly distributed across N = 3 stages:

f 3 8 2

© Digital Integrated Circuits2nd Inverter

 Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
N ln F
C L F Cin  f Cin with N 
ln f
t p 0 ln F  f  
t p  Nt p 0 F /   1 
1/ N
  
  ln f ln f 
t p t p 0 ln F ln f  1   f
  0
f  ln f 2

For  = 0, f = e, N = lnF f exp1   f 

© Digital Integrated Circuits2nd Inverter
 Optimum Effective Fanout f
Optimum f for given process defined by 
f exp1   f 
fopt = 3.6
for =1

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 Impact of Self-Loading on tp

No Self-Loading, =0 With Self-Loading =1

60.0

40.0
u/ln(u )

x=10,000

x=1000

20.0 x=100

x=10

0.0
1.0 3.0 5.0 7.0
u

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 Normalized delay function of F


t p  Nt p 0 1  N F /  

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 Buffer Design
N f tp
1 64 1 64 65

1 8 64 2 8 18

1 4 16 64 3 4 15

1 64 4 2.8 15.3
2.8 8 22.6

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 Power Dissipation

© Digital Integrated Circuits2nd Inverter

Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Leakage
Leaking diodes and transistors

© Digital Integrated Circuits2nd Inverter

 Dynamic Power Dissipation
Vdd

Vin Vout

CL

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f

Not a function of transistor sizes!

Need to reduce CL, Vdd, and f to reduce power.

© Digital Integrated Circuits2nd Inverter

Modification for Circuits with Reduced Swing
Vdd
Vdd

Vdd -Vt

CL

E 0  1 = CL  Vdd  Vdd – Vt 

Can exploit reduced swing to lower power

(e.g., reduced bit-line swing in memory)

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 Adiabatic Charging

2 2

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 Adiabatic Charging

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 Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E = C  V 2  n N 
N L dd
EN : the energy consumed for N clock cycles
n(N): the number of 0->1 transition in N clock cycles
EN  n N  2
P avg = lim --------  fclk =  lim ------------   C  Vdd  f clk
N  N N  N L
N 
  = lim n
------------
0 1 N  N

P =   C V 2f
avg 0 1 L dd clk

© Digital Integrated Circuits2nd Inverter

 Transistor Sizing for Minimum
Energy In Out

Cext
Cg1 1 f

 Goal: Minimize Energy of whole circuit

 Design parameters: f and VDD
 tp  tpref of circuit with f=1 and VDD =Vref
 f  F 
t p t p 0   1     1   

    f  
VDD
t p0 
VDD  VTE

© Digital Integrated Circuits2nd Inverter

 Transistor Sizing (2)
 Performance Constraint (=1)
 F  F
 2  f    2  f  
tp t p0  f  VDD Vref  VTE  f 
  1
t pref t p 0 ref 3  F  Vref VDD  VTE 3  F 
 Energy for single Transition
2
E VDD C g1 1   1  f  F 
2
E  VDD   2  2 f  F 
   
 
Eref  Vref   4  F 

© Digital Integrated Circuits2nd Inverter

 Transistor Sizing (3)
VDD=f(f) E/
Eref=f(f)
4 1.5

3.5
F=1
3
2

normalized energy
1
2.5
vdd (V)

2 5
1.5
0.5

1 10

0.5 20

0 0
1 2 3 4 5 6 7 1 2 3 4 5 6 7
f f

© Digital Integrated Circuits2nd Inverter

 Short Circuit Currents
Vdd

Vin Vout

CL

0.15

0.10
IVDD (mA)

0.05

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)

© Digital Integrated Circuits2nd Inverter

How to keep Short-Circuit Currents Low?

Short circuit current goes to zero if tfall >> trise,

but can’t do this for cascade logic, so ...
© Digital Integrated Circuits2nd Inverter
 Minimizing Short-Circuit Power
8

Pnorm
5
Vdd =3.3

4
Vdd =2.5
3

1
Vdd =1.5
0
0 1 2 3 4 5
tsin/tsout

© Digital Integrated Circuits2nd Inverter

 Leakage
Vdd

Vout

Drain Junction
Leakage

Sub-Threshold
Current

Sub-threshold current one of most compelling issues

Sub-Threshold Current Dominant Factor
in low-energy circuit design!

© Digital Integrated Circuits2nd Inverter

 Reverse-Biased Diode Leakage
GATE

p+ p+
N

Reverse Leakage Current

+
V
- dd

IDL = JS A

JS = JS
1-5pA/ mpA/m2
= 10-100
2
for a 1.2 m
at 25 degCMOS technology
C for 0.25m CMOS
JS doubles for every 9 deg C!
Js double with every 9oC increase in temperature

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 Subthreshold Leakage Component

© Digital Integrated Circuits2nd Inverter

 Static Power Consumption
Vdd

Istat
Vout

CL
Vin=5V

Pstat = P(In=1).Vdd . Istat

Wasted•energy … over dynamic consumption

Dominates
Should be avoided in almost all cases,
• Not a function of switching frequency
but could help reducing energy in others (e.g. sense amps)

© Digital Integrated Circuits2nd Inverter

 Principles for Power Reduction
 Prime choice: Reduce voltage!
 Recent years have seen an acceleration in
supply voltage reduction
 Design at very low voltages still open question
(0.6 … 0.9 V by 2010!)
 Reduce switching activity
 Reduce physical capacitance
 Device Sizing: for F=20
– fopt(energy)=3.53, fopt(performance)=4.47

© Digital Integrated Circuits2nd Inverter

 Impact of
Technology
Scaling

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 Goals of Technology Scaling
 Make things cheaper:
 Want to sell more functions (transistors)
per chip for the same money
 Build same products cheaper, sell the
same part for less money
 Price of a transistor has to be reduced
 But also want to be faster, smaller,
lower power

© Digital Integrated Circuits2nd Inverter

 Technology Scaling
 Goals of scaling the dimensions by 30%:
 Reduce gate delay by 30% (increase operating
frequency by 43%)
 Double transistor density
 Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
 Die size used to increase by 14% per
generation
 Technology generation spans 2-3 years

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 Technology Generations

© Digital Integrated Circuits2nd Inverter

 Technology Evolution (2000 data)

nternational Technology Roadmap for Semiconducto

Year of
1999 2000 2001 2004 2008 2011 2014
Introduction
Technology node
180 130 90 60 40 30
[nm]
Supply [V] 1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 0.3-0.6
Wiring levels 6-7 6-7 7 8 9 9-10 10
Max frequency 14.9
1.2 1.6-1.4 2.1-1.6 3.5-2 7.1-2.5 11-3
[GHz],Local-Global -3.6
Max P power [W] 90 106 130 160 171 177 186
Bat. power [W] 1.4 1.7 2.0 2.4 2.1 2.3 2.5

Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

© Digital Integrated Circuits2nd Inverter
 Technology Evolution (1999)

© Digital Integrated Circuits2nd Inverter

 ITRS Technology Roadmap
Acceleration Continues

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Technology Scaling (1)
2
10

Minimum Feature Size (micron)

1
10

0
10

-1
10

-2
10
1960 1970 1980 1990 2000 2010
Year

Minimum Feature Size

© Digital Integrated Circuits2nd Inverter
Technology Scaling (2)

Number of components per chip

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Technology Scaling (3)

tp decreases by 13%/year
50% every 5 years!

Propagation Delay
© Digital Integrated Circuits2nd Inverter
 Technology Scaling (4)

ears
100 x 1 .4 / 3 y 1000 
0 .7
Power Dissipation (W)

Power Density (mW/mm2 )

a rs
ye
10 3 

3
4 /


x 100

10
0.1
MPU
DSP
0.01 1
80 85 90 95 1 10
Scaling Factor 
Year （ normalized by 4m design rule）
(a) Power dissipation vs. year. (b) Power density vs. scaling factor.

From Kuroda
© Digital Integrated Circuits2nd Inverter
Technology Scaling Models
• Full Scaling (Constant Electrical Field)
ideal model — dimensions and voltage scale
together by the same factor S

• Fixed Voltage Scaling

most common model until recently —
only dimensions scale, voltages remain constant

• General Scaling
most realistic for todays situation —
voltages and dimensions scale with different factors

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Scaling Relationships for Long Channel Devices

© Digital Integrated Circuits2nd Inverter

 Transistor Scaling
(velocity-saturated devices)

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 Processor Scaling

P.Gelsinger: Processors for the New Millenium, ISSCC 2001

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 Processor Power

P.Gelsinger: Processors for the New Millenium, ISSCC 2001

© Digital Integrated Circuits2nd Inverter

 Processor Performance

P.Gelsinger: Processors for the New Millenium, ISSCC 2001

© Digital Integrated Circuits2nd Inverter

 2010 Outlook
 Performance 2X/16 months
 1 TIP (terra instructions/s)
 30 GHz clock
 Size
 No of transistors: 2 Billion
 Die: 40*40 mm
 Power
 10kW!!
 Leakage: 1/3 active Power
P.Gelsinger: Processors for the New Millenium, ISSCC 2001

© Digital Integrated Circuits2nd Inverter

 Some interesting questions
 What will cause this model to break?
 When will it break?
 Will the model gradually slow down?
 Power and power density
 Leakage
 Process Variation

© Digital Integrated Circuits2nd Inverter