Combinational Circuits

 A combinational logic circuit has:

• A set of m Boolean inputs,
• A set of n Boolean outputs, and
• n switching functions, each mapping the 2m input
combinations to an output such that the current output
depends only on the current input values
 A block diagram:
Combinatorial

Logic

Circuit

m Boolean Inputs
n Boolean Outputs
 Design Issues
Modern complex circuits and system involves a number of techniques and tools

for Effective and Efficient digital design.

 Design Hierarchy
 Top-Down Design
 Computer Aided Design
 Hardware Description Languages (HDL)
 Logic Synthesis
 Beginning Hierarchical Design
 To control the complexity of the function mapping inputs to
outputs:
• Decompose the function into smaller pieces called blocks
• Decompose each block’s function into smaller blocks, repeating as
necessary until all blocks are small enough
• Any block not decomposed is called a primitive block
• The collection of all blocks including the decomposed ones is a
hierarchy
 Example: 9-input parity tree (see next slide)
• Top Level: 9 inputs, one output
• 2nd Level: Four 3-bit odd parity trees in two levels
• 3rd Level: Two 2-bit exclusive-OR functions
• Primitives: Four 2-input NAND gates
• Design requires 4 X 2 X 4 = 32 2-input NAND gates
Hierarchy for Parity Tree Example
X0
X1
X2
9-Input
X3
X4 odd Z O
X5 function
X6 X0 A0
3-Input
X7
X8 X1 A1 odd B O
function
X A2
(a) Symbol for circuit 2

X 3
A0 A 0
3-Input 3-Input

X4 A1 odd B A odd B Z
O 1 O O
function function
X5 A2 A 2

X6 A0
3-Input

X7 A1 odd B O
function
X8 A2

(b) Circuit as interconnected 3-input odd

function blocks

A0

A1 B O

A2

(c) 3-input odd function circuit as

interconnected exclusive-OR

blocks

(d) Exclusive-OR block as interconnected

NANDs
 Reusable Functions
 Whenever possible, we try to decompose
a complex design into common, reusable
function blocks
 These blocks are
• verified and well-documented
• placed in libraries for future use
Top-Down versus Bottom-Up
 A top-down design proceeds from an abstract, high-level
specification to a more and more detailed design by
decomposition and successive refinement
 A bottom-up design starts with detailed primitive blocks
and combines them into larger and more complex
functional blocks
 Design usually proceeds top-down to known building
blocks ranging from complete CPUs to primitive logic
gates or electronic components.
 Much of the material in this chapter is devoted to
learning about combinational blocks used in top-down
design.
 Computer-Aided Design

 Design of complex systems and Integrated circuits by the use of CAD tool.
 Functional blocks, level of primitive, libraries of graphics symbols.
 Allow the behavior and timing of the hierarchical blocks are verified by logic
simulator to determine the output.
 Logic synthesizers provides the physical area information and delay parameters
for optimized design.
Hardware Description Languages

 Like programming languages, but specifically oriented to describing hardware

structures and behaviors.
 Represent parallel operation unlike serial operation in most programming.
 Structural description which describes an interconnection of components and
provide a uniform, portable representation for simulation.
 Can represent boolean equations, truth tables, complex operations.
Supports design verification, logic synthesis and provides intermediate level of

system description as RTL.

Standard hardware design language: VHDL and Verilog publised by IEEE

 Logic Synthesis

Transforms an RTL description of circuit into optimized storage elements and

combinational logic.

General directives may be given which specifies that area is to be minimized and

maximize speed.

First step: Translation of HDL description into an intermediate form

Second Step: Optimization( technology mapping)

 Analysis Procedure
Derivation of Boolean Function
1. Label all gate outputs that are a function only of input variables or their

complements with arbitrary symbols. Determine the Boolean functions for each

gate output.
2. Label the gates that are a function of input variables and previously labeled

gates with different arbitrary symbols. Find the Boolean function for the outputs

of these gates.
3. Repeat the process outlined in step 2 until the outputs of the circuit are obtained

in terms of the input variables.

Three inputs variables A, B, C and two binary outputs F1 and F2.
 Boolean functions: F2=AB+AC+BC
T1=A+B+C
T2=ABC
Now, T3=F2’T1
F1=T2+T2
So F1=T3+T2
=F2’T2+ABC=(AB+AC+BC)’(A+B+C)+ABC
=A’BC’+A’B’C+AB’C’+ABC
Derivation of Truth Table
 Determine the number of input variables in
the circuit. For n inputs, list the binary
numbers from 0 to 2n-1
 Break the circuit into small single-output
blocks by labeling each block output with an
arbitrary symbol.
 Obtain the truth table for the blocks with
functions that depend on input variables
only.
 Proceed to obtain the truth table for
blocks with functions that depend on
previously defined inputs and blocks
outputs until the columns for all circuit
outputs are determined.
 Logic Simulation
 Logic simulation is a fast, accurate method of
analyzing a combinational circuit for logic
waveforms, truth table but does not produce
Boolean function.
 HDL description generate a logic schematic.
 Validate the simulation by timing
information from the simulation.
 Design Procedure
1. Specification
• Write a specification for the circuit ( determine the
required numbers of input/outputs, & assign symbol to
each)
2. Formulation
• Derive a truth table or initial Boolean equations that
define the required relationships between the inputs and
outputs
3. Optimization
• Draw a logic diagram or provide a netlist for the resulting
circuit using ANDs, ORs, and inverters
Design Procedure
4. Logic Diagram
• Map the logic diagram or netlist to the
implementation technology selected
5. Verification
• Verify the correctness of the final design
manually or using simulation
 Design Example
1. Specification
• BCD to Excess-3 code converter
• Transforms BCD code for the decimal digits to
Excess-3 code for the decimal digits
• BCD code words for digits 0 through 9: 4-bit
patterns 0000 to 1001, respectively
• Excess-3 code words for digits 0 through 9: 4-bit
patterns consisting of 3 (binary 0011) added to
each BCD code word
• Implementation:
 multiple-level circuit
 Design Example (continued)
2. Formulation
• Conversion of 4-bit codes can be most easily
formulated by a truth table
• Variables Input BCD Output Excess-3
- BCD: ABCD WXYZ
A,B,C,D 0000 0011
• Variables 0001 0100
0010 0101
- Excess-3 0011 0110
W,X,Y,Z 0100 0111
• Don’t Cares 0101 1000
- BCD 1010 0110 1001
0111 1010
to 1111 1000 1011
1001 1011
 Design Example (continued)
3. Optimization z 1
C
1
y 1 1
C

a. 2-level using
0 1 3 2 0 1 3 2

1 1 1 1

K-maps
4 5 7 6 4 5 7 6

X X X X B X X X X B
12 13 15 14 12 13 15 14

W = A + BC + BD A 1
8 9
X
11
X
10
A 1
8 9
X
11
X
10

X = B’C+B’D + BC’D’
D D
Y = CD + C’D’
Z = D’
C C
x w
1 1 1
0 1 3 2 0 1 3 2

1 1 1 1
4 5 7 6 4 5 7 6

X X X X B X X X X B
12 13 15 14 12 13 15 14

A 1 X X A 1 1 X X
8 9 11 10 8 9 11 10

D D
Design Example (continued)
3. Optimization (continued)
W=A+B(C+D)
X=B’(C+D)+BC’D’
Y=(C D)’
Z=D’
Design Example (continued)
4. Logic Diagram
Basic Verification Methods
 Manual Logic Analysis
• Find the truth table or Boolean equations for the final circuit
• Compare the final circuit truth table with the specified truth
table, or
• Show that the Boolean equations for the final circuit are equal
to the specified Boolean equations
 Simulation
• Simulate the final circuit (or its netlist, possibly written as an
HDL) and the specified truth table, equations, or HDL
description using test input values that fully validate
correctness.
• The obvious test for a combinational circuit is application of all
possible “care” input combinations from the specification
 Verification Example: Simulation
 Run the simulation of the circuit for 120 ns
INPUTS
A
B
C
D
OUTPUTS
W
X
Y
Z

 Do 0the simulation output combinations

50 ns
match the 100 ns
original
truth table?
 Assignments
• Design a combinational circuit with three inputs and one

output. The output must be logic 1 when the binary value of the

inputs is less than 011(3) and logic 0 otherwise. Use only

NAND gates.
• Design a BCD to Seven Segment Decoder circuit. Use NOR

gate only in your final designed circuit.

• A logic circuit implements the following Boolean’s logic

function F=A’C+AC’D’, it is found that the circuit input

 Decoding
 A n-bit binary code can represent up to m=2n
elements:
m elements encoding n-bit binary code
(ex. 256 alpha-num. chars) (ex. 8-bit ASCII code)
decoding
 Decoding - the conversion of an n-bit input code
to an m-bit output code with
n ≤ m ≤ 2n such that each valid code word
produces a unique output code
D0
A0
n D1
n-2 m-elements
:
n bits : n
decoder ≤2
: :

An-1 Dm-1
 Decoder examples
 BCD to 7-segment decoder: a
a
b

decoder
b
 Binary to ASCII. BCD c

:
code
 Address decoder in a memory:
:

Row
Example: 4Mbit DRAM Decoder
1
1
MATRIX OF
22
No. of memory positions: 2 Row MEMORY

This requires 22 address bits: address

CELLS

N row address bits (ex. 11)

M column addr bit (ex. 11) one cell

N N
2
M
1 2
The address bits are decoded into actual
Column decoder
Read
memory locations
Write
Control M
1
Out In Column address

Data
2-to-4 line decoder

Table:

A 1 A 0 D 0 D D2 D
1 3
0
D0
A0 0
0 0 1 0 0 0
2-4 line 1
D1 0 1 0 1 0 0
Decoder
2
1 0 0 0 1 0
D2
1 ?
A1 1 1 0 0 0 1
3
D3
Logic expressions:
only one of the inputs is active D0 = A 1 A0

D1 = A 1 A0
minterms
D2 = A 1 A0

D3 = A 1 A0
2-to-4 Line Decoder circuit

A 0

A 1

D0 = A 1 A0

D1 = A 1 A0

D2 = A 1 A0

D3 = A 1 A0

Notice that the outputs of the decoder correspond to the minterms:

Di=mi
Decoder Expansion
 Larger decoders can be realized by
implementing each minterm using a single
AND gate:
• However for large decoders this requires
multiple input AND gates which is not always
feasible.
• Better to use a hierarchical approach: build
larger ones from smaller decoders.
 Approach:
• Output AND gates have only 2 inputs and
implement the minterms.
• The output AND gates are driven by two
decoders with their numbers of inputs either
equal or differing by 1.
 Decoder Expansion - Example 1
 3-to-8-line decoder
• Number of output ANDs = 8 A’1A’0 A2’A1’A0’

• Number of inputs: 3 A0
A2’A1’A0
A’1A0
2-4

Decoder A2’A1A0’
A1’A0
A1

A’1A’0 A2’A1A0
D0 A1A0

A0
A’1A0
2-4 D1 A’2
A2 A2A1’A0’
Decoder
AA0’ A2
A1 D2

A1A0 1-to-2

D3 decoder

A2A1A0

3-to-8 decoder
Further Decoder Expansion of
Example 1
Rule for building large decoders
 k-to-2k decoder:
• One needs 2k output AND gates
• If k can be divided by 2:
 use two k/2-to-2k/2 decoders
• If k cannot divided by 2:
 use a (k+1)/2 and
 use a (k-1)/2 decoder.
 Previous example: 3-to-8 decoder
(k=3):
• Use a 2-to-4 and a 1-to-2 decoder
Example : build a 4-to-16 decoder

 How many 2-input output AND gates?

 Which smaller decoders to use?
 Draw the circuit.
4-to-16 decoder
2
Use two 2-to-2 decoders A3’A2’A1’A0’
D0
A1’A0’ A3’A2’A1’A0
D0
D1
A0 A1’A0
2-4 D1 D2
Decoder A1A0’ A3’A2’A1A0
D2 D3
A1 A1A0 A3’A2A1’A0’
D4
D3

D0
A3’A2’ :

A2 A3’A2
:
2-4 D1

Decoder

D2
A3 A3A2
D14 A3A2A1A0’
D3
D15 A3A2A1A0
Decoder Expansion - Exercise 2
 5-to-32-line decoder
• Number of output ANDs = ?
• Number of inputs to decoders driving output
ANDs = ?
• Which decoders to use to drive the output
ANDs?
• Block diagram:
5-to-32-line decoder
A4’A3’ A2’A1’A0’
D0
A2’A1’A0’ D0
A2’A1’A0 A4’A3’ A2’A1’A0
A0 D1
D1
D2

3-8
D3 D2
A1
Decoder
D3

A2 D4
D7

D0
A4’A4’ D7

A3 A3’A2
2-4 D1

Decoder
:
A4 D2
A4A3
:
D30
D3 A2A1A0
A4A3
D31
Decoder Expansion - Example 2
 7-to-128-line decoder
• Number of output ANDs = ?
• Number of inputs to decoders driving
output ANDs = ?
• Closest possible split to equal
 Decoder with Enable
 Extra input EN:
 If EN = 1: act as a regular decoder 0
D0
A0
 If EN=0, all outputs are 0 2-4
D1
Decoder
D2
A1 1
D3
EN

 See truth table below for function

 Decoder with Enable: circuit
EN
Extra set

D0 of ands
A0 0
2-4
D1
Decoder
D2
A1 1
D3
EN

Regular decoder

If one considers EN an input, in that case the circuit can be viewed

as distributing value of signal EN(=IN) to 1 of 4 outputs: called a
demultiplexer: D0
0

EN=IN Demux 1
D1
2
D2
1 0
3
D3
A1 A0
Combinational Logic Implementation
- Decoder and OR Gates

 Implement m functions of n variables

with:
• Sum-of-minterms expressions
• One n-to-2n-line decoder
• m OR gates, one for each output
Example
 Design and implement a majority
function F(ABC) using a 3-to-8
decoder Indicate MSB, LSB
ABC F
 Truth table: 000 0
0
A
001 0 2 1

2
010 0
B 1 3
F
011 1 4

0 5
100 0 C
 Minterms: 101 1
6

• F=m(3,5,6,7) 110 1

 Implementation using
111 1 decoder:
 Exercise
 Implement the functions using a 3-to-8 decoder:

• F2(ABC)=m (0,2,3,5,6,7)

• F3=AB’ + BC

• F4(ABC)= A + B + C’
 Answer
• For F2(ABC)=m (0,2,3,5,6,7) implement

F2’=m(1,4): OR and INV= NOR gate with m1 and m4 as inputs.

• F3= AB’+BC = AB’(C+C’)+BC (A+A’)

= m5 + m4 + m7 + m3

• F4=A+B+C’:
now F4’=A’B’C=m1 Thus F4=m1’ (needs an inverter);otherwise:

F4=m0+m2+m3+m4+m5+m6+m7
 Exercise
Implement the function F using a 2-to-4 decoder and two tri-state buffers

F=C(AB+A’B’)
 Exercise - solution
Implement the function F using a 2-to-4 decoder and two tri-state buffers

F=C(AB+A’B’) = ABC + A’B’C

B 0
1 B’C F
A
1

2
0
C 3 BC
 Exercise

Can you also implement F using a 2-to-4 decoder with enable input and an OR gate?

F=C(AB+A’B’)
 Exercise - solution
1. Using a 2-to-4 decoder with enable input and an OR gate:

F=C(AB+A’B’) = ABC + A’B’C

EN

A’B’
A 0
1
1 F
2
0
B 3 AB
EN

C
 Exercise

Can you also implement F using a 2-to-4 decoder with enable input and an NOR gate?

F=C(AB+A’B’)
Encoders
 An encoder is a digital function that
performs the inverse operation of a
decoder.
 An encoder has 2n (or fewer) input lines
and n outputs lines.
 The output lines generate the binary code
corresponding to the input value.
 E.g. Octal to binary encoder
Encoding

D0
A0
D1
m-elements encoder n output
:
n :
≤2 bits
:
:
An-1
Dm-1

m elements encoding
n-bit binary code

decoding

D0
A0
D1
2-to-4 m-elements
:
n bits : n
decoder ≤2
: :

An-1 Dm-1
 Encoding
 Typically, an encoder converts a code
containing exactly one bit that is 1 to a binary
code corresponding to the position in which the
1 appears: ex. D1=1  output 0001
0
0 D0 0
1 A0 1
1 D1
encoder

2
1
3
: 0
0 :
2 :
0 : 0
An-1
0 Dm-1 n-1
m-1
0

 Examples: Octal-to-Binary encoder

 Other examples?
Example: A decimal-to-BCD encoder

D9 3
A3
9
D8
8
1 2 3 D7 7

6 A2
2
4 5 6
encoder

7 8 9 A1
1

0
A0
D0 0
0

 A decimal-to-BCD encoder
• Inputs: 10 bits corresponding to decimal digits 0 through 9, (D 0, …, D9)

• Outputs: 4 bits with BCD codes

• Function: If input bit Di is a 1, then the output (A 3, A2, A1, A0) is the BCD code for

i,
Truth table of the decimal-to-BCD
encoder
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0

0 0 0 0 0 0 0 0 0 1 0 0 0 0

0 0 0 0 0 0 0 0 1 0 0 0 0 1

0 0 0 0 0 0 0 1 0 0 0 0 1 0

0 0 0 0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 0 1 0 0 0 0 0 1 0 0

0 0 0 0 1 0 0 0 0 0 0 1 0 1

0 0 0 1 0 0 0 0 0 0 0 1 1 0

0 0 1 0 0 0 0 0 0 0 0 1 1 1

0 1 0 0 0 0 0 0 0 0 1 0 0 0

From table: 1 0 0 A3
0 = D8
0 + D9
0 0 0 0 0 We 1
made
0 use
0 of1 the fact that
A2 = D4 + D5 + D6 + D7 only one input can be “1” at

A1 = D2 + D3 + D6 + D7 one time

A0 = D1 + D3 + D5 + D7 + D9
Assignments
• Design the following Encoder circuit

• Octal to Binary Encoder.

• Decimal to BCD Encoder.

• Decimal to Binary Encoder

• ASCII to Binary Encoder

 Priority Encoder
 If more than one input value is 1, then the encoder
just designed does not work.
 An encoder that can accept all possible
combinations of input values and produce a
meaningful result is a priority encoder.
 Among the 1s that appear, it selects the most
significant input position (or the least significant
input position) containing a 1 and responds with the
corresponding binary code for that position.
 Combinational circuit that implements a priority
function.
D0 0
1

processor
A1
D1 1

To
?
D2 2
0 A0
D3 3
V
Priority Encoder Example
 Priority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest priority
is given to most significant 1 present - Code outputs A2, A1, A0
and V where V indicates at least one 1 present.

No. of Min- Inputs Outputs

terms/Row D4 D3 D2 D1 D0 A2 A1 A0 V

0 0 0 0 0 X X X 0
1
0 0 0 0 1 0 0 0 1
1 0
0 0 0 1 X0
1 0 0 1 1
2 1

4 0 0 1 X X 0 1 0 1

0 1 X X X 0 1 1 1
8
1 X X X X 1 0 0 1
16
Priority Encoder Example (continued)

One can use a K-map

to get equations, but
can be read directly
from table and
manually optimized if
careful:

A2 = D4

D4=
A1 D3 + D4D2D3

A0 =

V=
Priority Encoder Example (continued)

 Could use a K-map to get equations, but can be read

directly from table and manually optimized if careful:

A2 = D4

D4=
A1 D3 + D4D2D3 D4= F1, F1 = (D3 + D2)

A0 = D3D4
+ D1D4
= D3
(D3D2
+ D1) D4 D2

V = D4 + F1 + D1 + D0
Exercise: design a 4 input priority
encoder with active low inputs

Table:
D0 0
1
A1
D1 1 D3 D2 D1 D0 A1 A0 V
?
D2 2
0 A0 1 1 1 1 x x 0
D3 3
V 1 1 1 0 0 0 1

1 1 0 x 0 1 1

1 0 x x 1 0 1

0 x x x 1 1 1

Expressions:

A1 = D3.D2’ + D3’ = D2’ + D3’

A0 = D3D2D1’ + D3’ = D2.D1’ + D3’

V = (D3.D2.D1.D0)’
Selecting (multiplexers)
 Selecting of data or information is a critical
function in digital systems and computers
 Circuits that perform selecting have:
• A set of n information inputs from which the selection is
made
• A set of k control (select) lines for making the selection
• A single output
I0 0
I1 1
I2 2
k
n ≤ 2 inputs I3 3 OUT

In-1 k-1 .. 1 0
n-1

Sk-1..S1 S0

k select lines
Multiplexer equivalent

I0
0
I1
1 Out
I2 2

I3 3
1 0
(Ref.: F. Vahid, “Digital Design”, J. Wiley, 2007)

S1 S0
 Many uses of multiplexers
 In computers to select among signals
 To implement command: X
0
Y Z
if A=0 then Z=XY
1

else Z=XY
A
 Trip controller in a car to display mileage,
time, speed, etc.

clock (F. Vahid)

odometer 1 4:1

2
speed 3
Display
1 0
S1 S0

Push button
mileage
Example of a 4-input MUX
 4 inputs mux requires 2 select lines:
I0 I0
0 0
I1 I1 Out
1 Out 1
4:1
I2 2 I2 2

I3 3 I3 3
1 0

S1 S0
S1 S0

Table (condensed truth table):

S1 S0 OUT

0 0 I0

0 1 I1

1 0 I2

1 1 I3
4:1 MUX realization
 Expression for OUT
S1 S0 OUT

0 0 I0

OUT = S1S0 I0+ S1S0 I1+ S1S0 I2+ S1S0 I3 0 1 I1

1 0 I2
m0 m1 m2 m3
k 1 1 I3
2 -1

or OUT = Σ mi Ii

 Circuit implementation: SOP

i=0

• 4 AND gates (4 product terms)

• 2-to-4 line decoder (to generate the
minterms)
Example: 4-to-1-line Multiplexer
 2-to-22-line decoder
 22 x 2 AND-OR
Decoder
S1
Decoder
4 3 2 AND-OR
S0
S1
Decoder m0
S0

m1

I1
Y

m2 Y

I2
m3

I3
4:1 Quad Multiplexer
 Quad refers to the fact that each
input consists of a 4-bit wide signal
(vector)

I0[3:0] 4
0
I1[3:0] 1
4
Out [3:0]
4:1
I2[3:0] 2

I3[3:0] 3
1 0

S1 S0

Single inputs for the select signals

 Exercise
 Build a 8:1 MUX using two 4:1 and one 2:1 muxes

I0 0

I1 1
4:1
2
I2
3
I3 1 0
0
OUT

S1 S0
1

I4
0

I5 S2
1
4:1
I6 2

3
I7 1 0
Ex: S2S1S0=110 : select I6

S1 S0
 Multiplexer-based combinational circuits
realization- Approach 1
 A mux can be easily used to implement a
function defined by a truth table (lookup table)
 Indeed the output F of a mux is equal to:
k
2 -1

F = Σ mi Ii Example
i=0

Give the input Ii the A B OUT =F

value of 0 or 1 0 0 I0 0 m0

as shown in the truth table m1

0 1 I1 1
m2
0 0 1 0 I2 1
m3
1 1 F
4:1 1 1 I3 0
1 2

3 F= Σm(1,2)
0 1 0

A B
 Example: Gray to Binary Code
 Design a circuit to Gray Binary

convert a 3-bit Gray ABC xyz

0 0 0 0 0 0
code to a binary code 10 0 0 01

 The formulation gives 1 10 010

010 01 1
the truth table on the 01 1 10 0

right 1 1 1 101

 It is obvious from this 101 1 10

0 01 1 1 1
table that X = C and the
Y and Z are more complex
 Gray to Binary (continued)
 Rearrange the table so
that the input combinations Gray Binary
are in counting order ABC xyz
000 000
001 111
010 011
011 100
100 001
101 110
 Functions y and z can 110 010
be implemented using 111 101
a dual 8-to-1-line
multiplexer by:
• connecting A, B, and C to the multiplexer select inputs
• placing y and z on the two multiplexer outputs
• connecting their respective truth table values to the inputs
Gray to Binary (continued)
Gray Binary
ABC xyz 0
0
D10
D00
000 000 1
1 D01 D11
001 111
1 D12
010 011 1 D02

011 100 0 D03 0 D13

100 001 0 D04 1 D14

Y Out Z
101 110 1 D05
Out
0 D15
110 010 1 D06 0 D16
111 101 0 D07 1 D17

A S2 A S2
8-to-1 8-to-1
B S1 B S1
MUX MUX
S0 C S0
C
Multiplexer-based combinational circuits
- Approach 2

 One can further simplify the

implementation:
 Previous example:
Example

A B OUT F
B 0
0 0 I0 0 F
B

0 1 I1 1 1
B
1 0 I2 1 B

1 1 I3 0
A
Exercise 1 (cont)
 Implement the function
F(A,B,C)=Σm(0,1,2,5) using a 4:1 mux
A B C F

0 0 0 1 1

0 0 1 1 1 0

0 1 0 1 C C 1 F
4:1
C 2
0 1 1 0
0 3
1 0 0 0 C 1 0

1 0 1 1
A B
1 1 0 0 0

0 1 1 0
Assignments
 Design a Binary Multiplier logic circuit which multiplies 4-Bit by
3-Bit Binary numbers.
 Design a combinational circuit that accepts a 2-bit number and
generates a 4-bit binary number output equal to the square of the
input number.
 Design a combinational circuit that compares two 4-bit unsigned
numbers A and B to see whether they are equal. The circuit has
one output X, so that X=1 if A<B and X=0 if A≥B.
 Implement a binary full adder with a dual 4 to 1 line multiplexer
and a single inverter.
 Implement the following Boolean function with an 8 to 1 line
multiplexer and a single inverter.
F(A, B, C, D)=m(2,3,5,6,8,9,12,14)