DFT VLSI BASICS

REVANTH K
LOGIC GATES
• A logic gate is a device that acts as a building block for
digital circuits. Logic gates perform basic logical functions
fundamental to digital circuits.
Basic logic gates
• There are seven basic logic gates: AND, OR, XOR, NOT,
NAND, NOR and XNOR.
AND gate OR gate
NOT gate
• XOR gate NOR gate
•

• NAND gate XNOR gate

 MULTIPLEXER
• A multiplexer, also referred to as MUX, is a combination
logic circuit that is designed to accept multiple input signals
and transfer only one of them through the output line. In
simple words, a multiplexer is a digital logic device that
selects one-out-of-N (N = 2n) input data sources and
transmits the selected data to a single output line.
• The multiplexer is also called data selector as it selects one
Select Line
from several. Output (Y)
(S)

0 I0

1 I1
REALIZATION OF GATES USING
MUX
2-input AND gate using 2:1 mux NOT gate
using 2:1 mux

2-input OR gate using 2x1 mux:

2-input XOR gate using 2x1 mux

FLIP FLOP & LATCHES
Latch Flip-Flop

The latch is transparent – because the Flip-flop is a pair of latches (master and
input is directly connected to the output slave flop). Flip-flop is sensitive to pulse
when enable is high. It means Latch is transition. The signal only propagates
sensitive to pulse duration (also called through on the rising/falling edge (also
soft barrier) called hard barrier)

More Area (more gates) because the flip-

Less Area (less gates)
flop contains two latches.
Less Power (less gates) More Power (more gates)

Slow –
Fast – (The delay of a combinational logic path
(The longer combinational path can be of a design using edge-triggered flip-
compensated by shorter path delays in flops is always less than the clock period
the subsequent logic stages. That’s why, except for those specified as false paths
for higher performance, circuits designer and multiple-cycle paths. Hence the
are turning to latched-based design.) longest path of a design limits the circuit
performance.)
D & SR FLIPFLOP/LATCH

S R Latch
BLOCKING VS. NONBLOCKING IN
VERILOG

Blocking Assignments (=):

•Execute sequentially, one after the other like standard programming code.
•Each statement blocks the execution of the next until it completes.
•Commonly used in combinational logic modeling.

Non-Blocking Assignments (<=):

•Execute concurrently, allowing all right-hand side (RHS) expressions to be evaluated in parallel.
•The assignments take effect at the end of the time step.
•Preferred in sequential logic (e.g., within clocked always blocks).
• module block_nonblock();
• reg a, b, c, d, e, f;
// Blocking assignments
• initial begin
• a = #10 1'b1; // Time 10ns
• b = #20 1'b0; // Time 30ns
• c = #40 1'b1; // Time 70ns
• end
// Non-blocking assignments
• initial begin
• d <= #10 1'b1; // Scheduled for 10ns
• e <= #20 1'b0; // Scheduled for 20ns
• f <= #40 1'b1; // Scheduled for 40ns
• end
• endmodule
VHDL MODELLING STYLES: BEHAVIORAL,
DATAFLOW, STRUCTURAL
• An architecture can be written in one of three basic coding
styles:
(1) Dataflow (2) Behavioral (3) Structural.
The difference between these styles is based on the type of
concurrent statements used:
• A dataflow architecture uses only concurrent signal assignment
statements.
• A behavioral architecture uses only process statements.
• A structural architecture uses only component instantiation
statements.
Instead of writing an architecture exclusively in one of these
 DATAFLOW STYLE OF MODELLING:

• Dataflow style describes a system in terms

of how data flows through the system.
Data dependencies in the description
match those in a typical hardware
implementation.
• A dataflow description directly implies a
corresponding gate-level implementation.
• Dataflow descriptions consist of one or
more concurrent signal assignment
statements.
• E.g. Dataflow style half-adder description.
BEHAVIORAL STYLE OF MODELLING

• A behavioral description describes a system’s

behavior or function in an algorithmic fashion.
• Behavioral style is the most abstract style. The
description is abstract in the sense that it does not
directly imply a particular gate-level
implementation.
• Behavioral style consists of one or more process
statements. Each process statement is a single
concurrent statement that itself contains one or
more sequential statements.
• Sequential statements are executed sequentially by
a simulator, the same as the execution of
sequential statements in a conventional
programming language.
STRUCTURAL STYLE OF MODELLING
• In structural style of modelling, an entity is
described as a set of interconnected components.
• The top-level design entity’s architecture describes
the interconnection of lower-level design entities.
Each lower-level design entity can, in turn, be
described as an interconnection of design entities
at the next-lower level, and so on.
• Structural style is most useful and efficient when a
complex system is described as an interconnection
of moderately complex design entities. This
approach allows each design entity to be
independently designed and verified before being
used in the higher-level description.
COMBINATIONAL AND SEQUENTIAL CIRCUITS.

Combinational Circuits Sequential Circuits

A combinational circuit is a digital circuit type The sequential circuit is a digital circuit type whose
where the output is only a pure function of output relies not just on the current values of the
the present input. input signals it has but it depends on the past
sequence of inputs as well.
Another distinction between sequential An integrated storage unit for sequential circuits can
circuits and combinational circuits is that a store instant results.
memory device is absent in combinational
circuits.
A circuit’s output from a combined circuit On the other hand, the output of the sequential
relies on the input at present. circuit will depend on the recent outputs and current
input.
There’s no combinational clock present in a However, the possibility of a clock is there in the
circuit. sequential circuit.

Demultiplexer, decoder, full adder encoder, Registers and Flip Flops are a few examples of
and half adder are a few examples of sequential circuits.
combinatorial circuits.
 COUNTERS
• A counter is a digital circuit that counts the number of clock pulses or the number of transitions of
a particular signal. In VLSI (Very Large Scale Integration), counters are used in various
applications such as:
• Frequency division: Counters can be used to divide the frequency of a clock signal by a certain
ratio.
• Pulse counting: Counters can be used to count the number of pulses of a particular signal.
• Sequence generation: Counters can be used to generate a sequence of binary numbers.
• Types of Counters
• There are several types of counters used in VLSI, including:
• Asynchronous counters: These counters use a separate clock signal for each bit of the counter.
• Synchronous counters: These counters use a single clock signal for all bits of the counter.
CLOCK DIVIDER
• A clock divider is a digital circuit that reduces the frequency
of a clock signal by a specified ratio. This is achieved by
dividing the clock signal by a divisor, which can be an integer
or a non-integer value.
CLOCK GATING
• Technique to switch off the clock when not in
use. It reduces the switching activity and hence,
saves dynamic power, without affecting the
design functionality.
• When ‘en’ is 1: Clock goes to the next flop
• When ‘en’ is 0: Clock to the next flop is blocked
by AND gate.
Cons:
— Can cause glitches in the gated clock. (If the
change in ‘en’ occurs when clk is ‘1’ as given, it
causes glitches in the gated clock.)
LATCH BASED CLOCK GATING
Use a latch (level-sensitive) to create a glitch-free clock gating cell.

Glitch Free Behavior

• This is a modification of simplest clock gating, by introducing a
negative latch as shown. When clock is ‘1’, the latch doesn’t allow the
glitch in ‘en’ signal to pass to the latch output ‘Q’. It holds the previous
value when clk signal was ‘0’, hence eliminating the glitch in gated
clock.
ENCODER
• Encoder is a combinational circuit which is designed to perform the
inverse operation of the decoder. An encoder has n number of input
lines and m number of output lines. An encoder produces an m bit
binary code corresponding to the digital input number. The encoder
accepts an n input digital word and converts it into an m bit another
digital word.
Examples of encoders ::
• Priority encoders
• Decimal to BCD encoder
• Octal to binary encoder
• Hexadecimal to binary encoder
DECODER
• A decoder is a combinational circuit. It has n input and to a
maximum m = 2n outputs. Decoder is identical to a
demultiplexer without any data input. It performs operations
which are exactly opposite to those of an encoder.
Examples of decoders ::
• Code converters
• BCD to seven segment decoders
• Nixie tube decoders
• Relay actuator
VERILOG CODE FOR 4 TO 2 LINE ENCODER

• module encoder_4_2_test;
reg a,b,c,d;
wire x,y;

encoder_4_2 encoder_4_2_test(a,b,c,d,x,y);
initial

begin
#000 a=0; b=0;c=0;d=1;
#100 a=0; b=0;c=1;d=0;
#100 a=0; b=1;c=0;d=0;
#100 a=1; b=0;c=0;d=0;
end
initial
begin
$monitor($time,"a=%b,b=%b,c=%b,d=%b,x=%b,y=%b",a,b,c,d,x,y);
end
endmodule
VERILOG CODE FOR 2 TO 4 LINE DECODER

• module decoder_2_4_test;
reg a,b;
wire w,x,y,z;

decoder_2_4 decoder_2_4_test(a,b,w,x,y,z);
initial

begin
#000 a=0; b=0;
#100 a=0; b=1;
#100 a=1; b=0;
#100 a=1; b=1;
end
initial
begin
$monitor($time,"a=%b,b=%b,w=%b,x=%b,y=%b,z=%b",a,b,w,x,y,z);
end
endmodule
PHASE LOCKED LOOP
• A phase-locked loop consists of a phase detector and a voltage
controlled oscillator. The output of the phase detector is the input of the
voltage-controlled oscillator (VCO) and the output of the VCO is
connected to one of the inputs of a phase detector which is shown
below in the basic block diagram. When these two devices are feed to
each other the loop forms.
Phase Detector: produces a DC voltage proportional to the phase
difference between the input signal (fin) and the feedback signal (fout).
Low Pass Filter: eliminates the high-frequency component of the phase
detector's output, producing a DC voltage that represents the phase
difference.
Voltage-Controlled Oscillator (VCO): produces a signal with a
frequency that can be shifted by applying a DC voltage to it.
The output frequency of the VCO is controlled by the DC voltage from the
low pass filter, allowing the PLL to generate a signal with a frequency
that is locked to the reference frequency (fin).
REGISTER
• A Flip-flop is a 1 bit memory cell which can be used for storing the digital
data. To increase the storage capacity in terms of number of bits, you can
use a group of flip-flops. Such a group of flip-flops is known as a Register.
The n-bit register will consist of n number of flip-flop(s) and it is capable of
storing an n-bit word.
• The binary-data, in a register, can be transfered within itself from one flip-
flop to another. A shift register is a type of register that allows such data
transfers. Shift register has 4 modes of operations.
• Next, let us have a look at each register operation one by one.
• Serial-in serial-out
• Serial-in parallel-out
• Parallel-in serial-out
• Parallel-in parallel-out
SERIAL-IN SERIAL-OUT
• Let all the flip-flops be initially in the reset condition i.e. Q3 = Q2 = Q1 =
Q0 = 0. If an entry of a four-bit binary number 1 1 1 1 is made into the
register, this number should be applied to Din bit with the LSB bit
applied first. The D input of FF-3 i.e. D3 is connected to serial data input
Din. The output of FF-3 i.e. Q3 is connected to the input of the next flip-
flop i.e. D2, and so on.
SERIAL-IN PARALLEL-OUT
• In such types of operations, the data is entered serially and taken out in parallel
fashion.
• Data is loaded bit-by-bit. The output(s) are disabled as long as the data is loading.
• As soon as the data loading gets completed, all the flip-flops contain their required
data. The output(s) are enabled so that all the loaded data is made available over
all the output lines at the same time.
• 4 clock cycles are required to load a four-bit word. Hence the speed of operation of
SIPO mode is the same as that of the SISO mode.
PARALLEL-IN SERIAL-OUT
• Data bits enter in a parallel fashion.
• The circuit, shown below, is a four-bit parallel-in serial-out register.
• Output of the previous flip Flop is connected to the input of the next one via a
combinational circuit.
• The binary input data bits B0, B1, B2, B3 are applied through the same combinational
logic circuit.
• There are two modes in which this circuit can work, namely - shift mode and load
mode
PARALLEL-IN PARALLEL-OUT
• Here, the 4-bit binary datda inputs B0, B1, B2, B3 are applied
to the data inputs D0, D1, D2, D3, respectively, of the four flip-
flops. When a negative edge of the clock is triggered, then the
flip-flops get loaded with the input binary bits simultaneously.
The loaded bits appear at the output side, simultaneously, as
well. Only the clock pulse is essential to load all the binary
bits.
THE END