Unit 5

VLSI Testing
Departmental core subject for
B. Tech Electronics & E&TC students

Pesenter: Shilpa K. Rudrawar

Assistant Professor,
School of Electrical
Engineering ,MITAOE, Pune
skrudrawar@etx.maepune.ac.in
 What is Design for Testability, &
why we need it?
Problems with manufacturing ICs:

Today, semiconductors lie at the heart of ongoing advances across the

electronics industry. The introduction of new technologies, especially
nanometer technologies with 14 nm or smaller geometry, has allowed the
semiconductor industry to keep pace with increased performance-capacity
demands from consumers. This has brightened the prospects for future
industry growth.

However, new technologies come with new challenges. Smaller die sizes
increase the probability of some errors. Errors in ICs are highly
undesirable. Here’s a list of some possible issues that arise while
manufacturing chips.

Shilpa K. Rudrawar
 Issues that arise while
manufacturing chips
Density Issue: Fabrication processes have become quite complicated with the
advent of deep-submicron design technologies.
Software Issue: Moreover, apart from fabrication, there can even be errors in
the translation process due to the bugs in CAD software tools used to design
the chip.
Application Issue: There are several critical applications, in which we can’t
afford to have faults in the chip at any cost. For example, in medical or
healthcare applications
Maintenance Issue: In case of any future failure, for repairing or
maintenance, we need to identify the proper coordinates of fault. Since PCB
sizes are also decreasing, multi-meter testing isn’t a viable option anymore.
Business Issue: If designed chips are found to be faulty, then it transforms
into a substantial loss and penalty for the company.

Shilpa K. Rudrawar
 Importance of Testing

 According to Moore’s law feature size is decreasing.

 Defects are unavoidable.
 Testing is required to guarantee fault-free chips.
 Product quality depends on the following parameters,
 Test cost
 Test quality
 Test time
 DFT – “The game changer”

Shilpa K. Rudrawar
 Sources of Faults in ICs
n
 Here are a few possible sources of faults:

 In the fabrication process like missing contact windows, parasitic

transistors, etc.
 Defects in the materials like cracks or imperfections in the substrate,
surface
impurities, etc.
 Aging caused by Dielectric breakdown, electron migration, etc.
 During packaging like Contact degradation, disconnection, etc

Shilpa K. Rudrawar
 What is Design For Testability,
& why we need it?

Shilpa K. Rudrawar
 What is DFT?

 Design For Testability refers to hardware design styles, or added hardware

that reduces test generation complexity.
 Philosophy of DFT is Murphy's law:- “Whatever can go wrong, will go wrong.”
 Motivation:- : Test generation complexity increases exponentially with the
size of the circuit.
 Basically DFT enables the manufacturing test.
 It is a structural technique, which facilitates a design to become testable
after production .

Shilpa K. Rudrawar
 Need of DFT: Levels of
Testing  Testing is carried out at various levels:

 Chip-level, when chips are manufactured.

 Board-level, when chips are integrated on the boards.

 System-level, when several boards are assembled together.

 There is an empirical rule of thumb that it is ten times more expensive to

test a device as we move to the next higher level (chip → board →
system).
 As we move to higher levels, more components are integrated, which makes
the fault detection and localization much more difficult and expensive

Shilpa K. Rudrawar
 Need of DFT

 To increase Productivity:
– Shorter time-to-market
– Reduced design cycle
– Reduced cost
 To improve Quality:
– Reduced Defects per million (DPM)
– Improved quality of test

Shilpa K. Rudrawar
 Faults
 Two key concepts are of interest here, these are :
 Controllability
 Observability
 1. Controllability - Being able to set up known internal states.
 2. Combinatorial Testability - Being able to generate all states to fully
exercise all
combinations of circuit states.
 3. Observability - Being able to observe the effects of a state change as it
occurs Internal nodes
(preferably at the system primary outputs).

Shilpa K. Rudrawar
 Verification Vs Testing
What is the difference between Verification and Testing?
Verification proves the correctness and logical functionality of the
design prefabrication. The process is done after the RTL (Register Transfer
Logic) design is coded with hardware description languages like VHDL or
Verilog. It is done using a test bench in a high-level language. This is performed
only once before the actual manufacturing of chip. In industry, this is done
using formal verification processes like UVM (Universal Verification
Methodology) using System Verilog. Verification is a vast topic on its own and
we will cover it in this VLSI track and link it here soon.
In contrast, testing tries to guarantee the correctness of the
manufactured chips at every abstraction level of the chip design
process. Testing needs to be performed on each manufactured chip because
each one of them has an equal probability of being faulty during the fabrication
or packaging process. By doing testing, we are improving the quality of the
Shilpa K. Rudrawar devices that are being sold in the market.
 Verification Vs Testing
Verification Testing

Verifies correctness of the

Verifies correctness of the design.
manufactured hardware.

Two-part process:
• Test generation: software
process executed once during
Performed by simulation, hardware
design. Performed only once.
emulation, or formal methods.
• Test application: electrical tests
applied to hardware. Performed
multiple times.

Performed once prior to

Test application is performed on every
manufacturing.
manufactured device.

Shilpa K. Rudrawar Responsible for the quality of design. Responsible for the quality of devices.
 Important Concept

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 Testing Combinational circuit

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 Testing Combinational circuit

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 Testing AND-OR Network

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 Scan Testing

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 Testing Sequential Circuits

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 Scan Testing

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 Scan Testing

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 Scan Testing

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 Boundary Scan

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 Boundary Scan

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 Boundary Scan

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 BIST-Built In Self Test

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 LFSR

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 Happy Learning!!!!
Shilpa K. Rudrawar