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8255 Ppi

The document discusses the interfacing of microprocessors with I/O devices, focusing on memory-mapped I/O and various peripheral controller chips developed by Intel, such as the 8255 Programmable Peripheral Interface (PPI). It details the 8255A's structure, programming modes, and applications, including controlling a 7-segment display and keyboard input. The document also includes examples of programming and interfacing techniques for these devices.

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9 views26 pages

8255 Ppi

The document discusses the interfacing of microprocessors with I/O devices, focusing on memory-mapped I/O and various peripheral controller chips developed by Intel, such as the 8255 Programmable Peripheral Interface (PPI). It details the 8255A's structure, programming modes, and applications, including controlling a 7-segment display and keyboard input. The document also includes examples of programming and interfacing techniques for these devices.

Uploaded by

rajshuklafirst88
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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UNIT-5

I/O
• Any microprocessor need to be interfaced with I/O
devices.
• The I/O address is 16 bit.
Memory mapped I/O
I/O Map
Parallel Printer Interface example
Peripheral Controllers
• Intel has developed several peripheral controller chips
designed to support its processors.
• The goal is to give a complete I/O interface in one chip.
• Examples:
• 8255 is Programmable Peripheral Interface (PPI).
• 8259 is Programmable Interrupt Controller (PIC)
• 8253/8254 is Programmable Interval Timer (PIT)
• 8237 is Programmable DMA controller.
8255A
• Is one of the peripheral controller chips designed to
support its processors.
• 8255 is Programmable Peripheral Interface (PPI).
• It is a general purpose parallel I/O Interfacing
device.
• It provides 24 I/O lines organized in three 8-bit I/O
ports in one 40-pin package.
• The ports are usually labeled A,B, and C.
fig 8.11
FIGURE 8-11 8255 programmable peripheral interface (PPI). Twenty-four I/O pins are provided grouped as three 8-bit I/O ports. There is
one 8-bit control port. (Courtesy of Intel Corporation.)
Size of ports
• Ports A and B can be programmed as an 8-bit input
or output port.
• In port C each nibble (four bits) can be programmed
separately to be a 4-bit input or output port.
• Only the above size of ports (byte or nibble) can be
programmed. For Example, individual bit in a port
cannot be programmed.
• However, what make 8254 a versatile devise is its
programming modes
Programming modes
• Mode 0: the 8255A is programmed to look like
three simple I/O ports.
• Mode 1: the 8255A is programmed to have two
handshaking I/O ports.
• Mode 1: the 8255A is programmed to have one
bidirectional port with five handshaking signals.
• The modes can be intermixed, for example, port A
is programmed to operate in mode 2, while port B
operates in mode 0.
• bit set/reset mode allows individual bits of port C to
be set or reset for control purposes.
FIGURE 8-12 Interfacing the 8255 to the 386/486 processors. The four PPI ports are mapped to addresses 0, 4, 8, and C.
8255

A1 A0 RD WR CS Direction
0 0 0 1 0 PORT A to data bus
0 1 0 1 0 PORT B to data bus
1 0 0 1 0 PORT C to data bus

0 0 1 0 0 data bus to PORT A


0 1 1 0 0 data bus to PORT B
1 0 1 0 0 data bus to PORT C
1 1 1 0 0 data bus to control

x x x x 1 data bus in 3rd state


1 1 0 1 0 illegal condition
x x 1 1 0 data bus in 3rd state
8255
FIGURE 8-13 Two types of 8255A control bytes. (a) When bit 7 = 0, a bit set/reset operation is indicated; (b) When bit 7 = 1, any of the
modes 0, 1, or 2 can be programmed.
FIGURE 8-14 Interfacing a 16-key switch matrix to the 8255A (assumed interfaced to the 386/486 circuit shown in Figure 8-12). Port A
is programmed as a mode 0 input port and port C (upper) as a mode 0 output port.
FIGURE 8-15 Flowchart of the process required to detect a key closure, debounce the key, and encode with a value between 0 and F.
FIGURE 8-17 Block diagram and pin descriptions for the 8254 programmable interval timer. Three separate timers/counters are provided.
(Courtesy of Intel Corporation.)
FIGURE 8-18 Interfacing the 8254 to the three-bus architecture of the 8088 processor. Four I/O ports are required. The port addresses and
connections shown correspond to those used in the IBM PC.
FIGURE 8-19 8254 control word. The standard form is used to specify the operating mode. The counter latch and read-back commands
are used when the present count or status is to be read.
Applications:7 Segment Display Control

20
• This program displays 5 hexadecimal digits on the 7-
segment LED display units connected to the 8255 PPI
• .DATA
• MSG DB 0EH,0EH,4,1,1
• ;------ code segment ------
• .CODE
• MAIN: MOV AX,@DATA
• MOV DS,AX
• MOV DX,303H
• MOV AL,10000000B
• OUT DX,AL
• START: MOV SI,OFFSET MSG
• MOV DI,0
• MOV BL,00010000B
21
• NEXT: MOV BH,[SI+DI]
• CALL DISPLAY ;CALL THE DISPLAY SUBROUTINE
• SHR BL,1
• INC DI
• CMP DI,4
• JNE NEXT
• JMP START
• DISPLAY: MOV DX,300H ;DISPLAY SUBROUTINE
• MOV AL,BL
• OUT DX,AL
• MOV DX,301H
• MOV AL,BH
• OUT DX,AL
• RET
• END MAIN

22
Application 2: Keyboard Control

23
• This program reads a keystroke from the 64-key keyboard connected to the PPI
• .DATA
• LETTERS DB
‘0123456789ABCDEFGHIJKLMNOPRSTUVWXYZabcdefghijklmnopqrstuv
wxyz.?’
• ;------ code segment ------
• .CODE
• MAIN: MOV AX,@DATA
• MOV DS,AX
• MOV DX,303H
• MOV AL,10000010B
• OUT DX,AL
• MOV BL,11111110B

24
• SCAN: ROR BL
• MOV AL,BL
• MOV DX,300H
• OUT DX,AL
• CMP AL,11111111B
• JE SCAN
• PUSH BX
• MOV DI,0
• NEXT: SHL BL,1
• JNC FINISHC
• INC DI
• JMP NEXT

25
• FINISHC: SHL AL,1
• JNC FINISHR
• ADD DI,8
• JMP NEXT
• FINISHR: MOV SI,OFFSET LETTERS
• MOV DL,[SI+DI]
• MOV AH,2
• INT 21H
• POP BX
• JMP SCAN
• END MAIN

26

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