Scribd
Upload
87 views20 pages

Design of The Cic Decimation Filter Based On Sopc Builder

This document discusses the design of a CIC decimation filter for a software defined radio application implemented on an FPGA. It presents a 3-stage CIC decimation filter architecture using an integrator, comb filter, and NCO. The CIC filter allows for large sampling rate conversions without multipliers. The document proposes using this special CIC filter architecture to address the problem of increasing bandwidth demands in software defined radios. It summarizes the advantages of CIC filters for FPGA implementation including no multipliers or storage needed and high customizability.

Uploaded by

Manu Kousar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
87 views20 pages

Design of The Cic Decimation Filter Based On Sopc Builder

This document discusses the design of a CIC decimation filter for a software defined radio application implemented on an FPGA. It presents a 3-stage CIC decimation filter architecture using an integrator, comb filter, and NCO. The CIC filter allows for large sampling rate conversions without multipliers. The document proposes using this special CIC filter architecture to address the problem of increasing bandwidth demands in software defined radios. It summarizes the advantages of CIC filters for FPGA implementation including no multipliers or storage needed and high customizability.

Uploaded by

Manu Kousar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 20

DESIGN OF THE CIC DECIMATION FILTER BASED ON SOPC BUILDER

Under the Esteemed Guidance of Sri. SK.KHAMURUDDEEN M.Tech Assistant Professor Department of ECE By B.SHILPA 09E51D5704

Aim of the project

Implementation of digital down converter (DDC) for FPGA based software defined radio application.
DDC is one of the core technology in SDR

Three stage CIC decimating filter

Sri Indu Engg College

4/25/2012

Integrator

Comb

General Block Diagram Of DDC


Antenna
Digital Mixer

LNA

RF AMP

ADC

NCO

Digital down converter and CIC filters

NCO

CIC (cascade integer comb) filter


A CIC filter is a special class of linear phase, finite

impulse response (FIR) filter. CIC filters do not require multipliers . CIC filters are used in multirate systems with large sampling frequency conversion .

NCO technique

NCO technique

Applications
all digital software defined radios

FPGA based multi rate signal processing system.


3G base station equipment.

Advantages
No multipliers are required.

No storage is required.
Customization is possible to very high degree FPGA is more suitable for implementing CIC

filters etc .

Disadvantages
The NCO based technique cant give frequency

sweep for all the frequencies. NCO based technique used ROM for SIN and COS generation

Current problem and proposed solution


Current problem:
The software defined radio bandwidths are increasing day by day.
Conventional FIR Filter and its modified architecture cannot work at high bandwidths.

proposed solution: A special architecture is called cascaded integrator comb filter. Complete FPGA implementation and demonstration on xilinx FPGA

References
IEEE - Down-Sample Design under Special Condition

in High-Speed All-Digital System


Hongwei Sun Jinshu Chen Dept. of Electron. Eng., Tsinghua Univ.Beijing, Beijing;

IEEE - FPGA design of arbitrary down-sampler


Jorgovanovic, M. Pajic, M. Kvascev, G. Popovic, J. Dept. of Electron., Belgrade Univ., Belgrade;

14

Sri Indu Engg College

4/25/2012

15

Sri Indu Engg College

4/25/2012

16

Sri Indu Engg College

4/25/2012

17

Sri Indu Engg College

4/25/2012

Conclusion& Future scope

The main application of DDC becomes the front end of software defined radio. The CIC architecture is suitable when input is coming at very high and required decimation factor is also low. CIC decimation filter component can be implemented successfully based on FPGA. CIC decimation filter component are programmable , Reliable and portable.

Tools and hardware


Simulation software

- Modelsim Xilinx Edition - Xilinx ISE 10.2 - Xilinx Chipscope

(MXE) Synthesis, P&R On chip verificaiton

Hardware

Xilinx Spartan 3 Family FPGA

board

References
IEEE - Down-Sample Design under Special Condition

in High-Speed All-Digital System


Hongwei Sun Jinshu Chen Dept. of Electron. Eng., Tsinghua Univ.Beijing, Beijing;

IEEE - FPGA design of arbitrary down-sampler


Jorgovanovic, M. Pajic, M. Kvascev, G. Popovic, J. Dept. of Electron., Belgrade Univ., Belgrade;

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy