- Use Verilog/System Verilog for design
- Always write a Testbench for a design
- Testbench should be self-checking test bench
- Testbench should use task for sending input data to the DUT
- Half Adder
- 1-bit Full Adder
- 1-bit Full Adder using Half Adder
- 4-bit full adder using Half Adder
- Mux using Case statement
- Mux using with the use logical expression
- Mux using Conditional operator
- ALU
- D Flip Flop with synchronous reset
- D Flip Flop with asynchronous reset
- Sequence Detector using Mealy machine (1101, Non-Overlapping)
- Sequence Detector using Moore machine (1101, Non-Overlapping)
- Sequence Detector using Mealy machine (1101, Overlapping)
- Sequence Detector using Moore machine (1101, Overlapping)
- Count the Number of 1s
- Binary to Gray Conversion
- Up Down Counter
- Random Counter
- Clock Divider
- PIPO
- n bit universal shift register
- 4 bit LFSR
- Custom Design
- Single port RAM (128x8)
- Dual port RAM (128x8)
- Synchronous FIFO
- Asynchronous FIFO
- 8x8 Sequential Multiplier
- 64 bit Pipelined Multiplier