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L4 integration: Adapted DMA to STM32L4 MCU series. #1916
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} dma_descr_t; | ||
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#define DMA_TX_TRANSFER DMA_MEMORY_TO_PERIPH | ||
#define DMA_RX_TRANSFER DMA_PERIPH_TO_MEMORY |
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@tobbad why did you declare these 2 macros? Why not just use DMA_MEMORY_TO_PERIPH and DMA_PERIPH_TO_MEMORY directly? To me, these are much clearer in their meaning than tx/rx.
The way you have written the code is that each periph defines a As an alternative, how about the following: expose each entry of the
Does that make sense? |
Thank you - good point. I was as well not satisfied with my solution. Sometimes you have different alternatives for a periphery. Shall I call them eg. |
If they're not used, don't declare them, just leave them as commented-out code in case they are needed later. Otherwise, if they are used, put a postfix of |
I have now a solution at hand and debugging it. Is there an automated build, deploy and test framework for directly testing the code on a hardware? For the DMA I started to build some code which:
Is there a function in mp where I can get the information which is returned during a cold reset eg:
What I am interested in is the version, date, board and CPU information. |
Try os.uname() |
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Thank you. I modified the PR according to your suggestions and collected all concerned file in this PR. I did some test (spi/i2c transfer on stm32f4disco and stm32l476disco) which passed. I hope that it can be merged now. |
I see that there are modifications to adc.c. Are they relevant to DMA? If not can you please separate the ADC changes into a separate commit (can be within this PR, just a separate commit to the DMA changes). Thanks! |
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Ops - that somehow sneaked in. The adc changes are already merged in d49a547. I did an update. |
#define DMA2_ENABLE_MASK 0xff00 // Bits in dma_enable_mask corresponding to DMA2 | ||
#define DMA_INVALID_CHANNEL 0xff // Value stored in dma_last_channel which means invalid | ||
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#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7) | ||
#define DMA_CHANNEL_AS_UINT8(dma_channel) (((dma_channel) & DMA_SxCR_CHSEL) >> 24) |
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@tobbad this macro is now wrong (or it's called incorrectly) because the argument is a dma_id_t which is not a channel. So this macro will always evaluate to 0 for the F4/F7.
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Thanks. But this macro is anyway wrong. In the data sheet the channel selection bits start a position 25 so the shift should be 25.
The macro should return the Stream number on f4/f7 which is in the range 0..7 and the channel number on l4 which is in the range 1..7. If we keep it simple we can use for both cases the macro
#define DMA_CHANNEL_AS_UINT8(dma_descr) ((dma_descr->id) % NSTREAMS_PER_CONTROLLER)
If would like to really have the values 1..7 instead of 0..6 for L4 we have to adapt the Macro accordingly.
I make the simple modification and re-push the stuff.
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@@ -33,9 +33,145 @@ | |||
#include "py/obj.h" | |||
#include "irq.h" | |||
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#define NSTREAMS_PER_CONTROLLER_LOG2 (3) | |||
#define NSTREAMS_PER_CONTROLLER (1 << NSTREAMS_PER_CONTROLLER_LOG2) |
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As NSTREAMS_PER_CONTROLLER_LOG2 is 3 for F-series we have 8 streams. but on L4 there are only 7 streams. The use of this #define in dma_tickle is therefore no more possible. Therefore I removed NSTREAMS_PER_CONTROLLER_LOG2.
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.MemBurst = DMA_MBURST_INC4, | ||
.PeriphBurst = DMA_PBURST_INC4, | ||
}; | ||
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Moved to dma.c
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Updated the code and did some clean ups. Did some simple i2c/spi test on stm32f4disco, stm32F429disco, stm32l4Disco, limifrog. |
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I did a little bit of tidying up (mostly white space changes and reordering some things in dma.c) and merged it in e64032d. Thank you! |
Removed warning box regarding SAMD21 builds
This is the 5th PR in a series (#1888, #1890, #1903, #1904 ) of PR to support the STM32L4 series in micropython. (see http://forum.micropython.org/viewtopic.php?f=12&t=1332&sid=64e2f63af49643c3edee159171f4a365)
The topic is to change the dma code in a way, that the structure
DMA_Stream_TypeDef
(which is similar toDMA_Channel_TypeDef
on stm32l4) is no more used outside of dma.c as this structure only exists for F4 series. Therefore I introduced a new structure (dma_descr_t
) which handles all dma specific stuff for configuration. Further the periphery (spi, i2c, sdcard, dac) does not need to know the internals of the dma.As a consequence a Periphery just asks for a dma to it self (defined by the enum
periphery_t
in dma.h) which instance of it self, and the direction of data transport. The DMA module then decides upon the Stream/Channel (stm32f4) or Channel/Request (stm32l4) should be used. These configuration are captured in the dma_transfer_info structure within dma.c. Further the initial setting (DMA_InitTypeDefsdma_init_struct_spi_i2c
anddma_init_struct_sdio
) is as well centralized in dma.c as these are as well MCU series specific.This fix should work without the merge of the earlier PRs.