L4 integration: Modifications to main. #1938
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tannewt
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Jun 12, 2019
…er-2019-06-11 Merge latest 4.0.x changes to master
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This is a PR in a series (#1888, #1890, #1903, #1904, #1916, #1917, #1918, #1919, #1920, #1921, #1922, #1924, #1925, #1929, #1937 ) of PR to support the STM32L4 series in micropython. (see http://forum.micropython.org/viewtopic.php?f=12&t=1332&sid=64e2f63af49643c3edee159171f4a365)
The macro
__CCMDATARAMEN_CLK_ENABLEis defined as__HAL_RCC_CCMDATARAMEN_CLK_ENABLEin stm32_hal_legacy.h on the l4 but on l4__HAL_RCC_CCMDATARAMEN_CLK_ENABLEcan not be resolved. Therefore I do not use this code on L4.I use SRAM2 on L4 for storage cache which is clocked in run mode (See table 20 in RM0351, STM32l4 reference manual from October 2015).