A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing

Pham, Xuan Thanh; Nguyen, Ngoc Tan; Nguyen, Van Truong; Lee, Jong-Wook

doi:10.3390/s20072059

Open AccessArticle

A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing

School of Electronics and Information, Information and Communication System-on-chip (SoC) Research Center, Kyung Hee University, Yongin 17104, Korea

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Author to whom correspondence should be addressed.

Sensors 2020, 20(7), 2059; https://doi.org/10.3390/s20072059

Submission received: 3 March 2020 / Revised: 28 March 2020 / Accepted: 2 April 2020 / Published: 6 April 2020

(This article belongs to the Section Electronic Sensors)

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Abstract

:

To realize an ultra-low-power and low-noise instrumentation amplifier (IA) for neural and biopotential signal sensing, we investigate two design techniques. The first technique uses a noise-efficient DC servo loop (DSL), which has been shown to be a high noise contributor. The proposed approach offers several advantages: (i) both the electrode offset and the input offset are rejected, (ii) a large capacitor is not needed in the DSL, (iii) by removing the charge dividing effect, the input-referred noise (IRN) is reduced, (iv) the noise from the DSL is further reduced by the gain of the first stage and by the transconductance ratio, and (v) the proposed DSL allows interfacing with a squeezed-inverter (SQI) stage. The proposed technique reduces the noise from the DSL to 12.5% of the overall noise. The second technique is to optimize noise performance using an SQI stage. Because the SQI stage is biased at a saturation limit of 2V_DSAT, the bias current can be increased to reduce noise while maintaining low power consumption. The challenge of handling the mismatch in the SQI stage is addressed using a shared common-mode feedback (CMFB) loop, which achieves a common-mode rejection ratio (CMRR) of 105 dB. Using the proposed technique, a capacitively-coupled chopper instrumentation amplifier (CCIA) was fabricated using a 0.18-µm CMOS process. The measured result of the CCIA shows a relatively low noise density of 88 nV/rtHz and an integrated noise of 1.5 µV_rms. These results correspond to a favorable noise efficiency factor (NEF) of 5.9 and a power efficiency factor (PEF) of 11.4.

Keywords:

ultra-low power; instrumentation amplifier; body control; electrode offset; dc servo loop; input-referred noise

1. Introduction

Recently, there is a growing interest in wearable, portable, and personal health monitoring. By detecting abnormal health conditions during daily monitoring, this approach provides a new method of preventive healthcare. Monitoring human biopotential and neural signals is also important for early diagnosis and medical treatment [1]. Concerning the biopotential monitoring applications, sensors and their interfaces providing high-quality signals are of great importance. Besides, these sensor devices demand both long operating time and a compact form factor. A battery is widely used, however, it requires frequent battery recharging or replacement, and there is a limit in its size for some applications such as implantable sensors. To achieve a compact form factor by reducing the volume of the battery, low power consumption is in great demand for wearable and portable sensor devices.

Signals from humans have an amplitude of around 1 mV for an electrocardiogram (ECG) and from 10 to 100 µV for an electroencephalogram (EEG) over a frequency band from 0.5 to 150 Hz [2]. The local field potential (LFP) has a typical amplitude of 1 mV over 1 to 200 Hz. These low-frequency signals must first be amplified before any signal processing can be applied. One issue with amplification is the overlap of these signals with 1/f noise. To mitigate the effect of 1/f noise, a chopping technique can be applied for instrumentation amplifiers (IAs) [3,4,5,6,7,8,9,10,11,12]. Another issue is the electrode offset voltage V_EOS generated at the tissue-electrode interface by electrochemical effects. To reject V_EOS, a DC servo loop (DSL) has been used in a capacitively-coupled chopper instrumentation amplifier (CCIA) [3]. This approach has the advantage of removing bulky external capacitors. However, the DSL achieves the V_EOS rejection by increased input-referred noise (IRN). The IRN

\bar{V_{n, in}^{2}}

of a CCIA can be expressed as [3]

\bar{V_{n, in}^{2}} = {(\frac{C_{in} + C_{fb} + C_{hp} + C_{P}}{C_{in}})}^{2} \bar{V_{n, in, Gm}^{2}}

(1)

where

\bar{V_{n, in, Gm}^{2}}

represents the input-referred noise of a transconductor. The C_in, C_fb, and C_P are the input, feedback, and parasitic capacitors that are connected to the input of the CCIA, respectively. The C_hp is the capacitor in the DSL which is used to create a high-pass corner to reject V_EOS. When a large C_hp is used, the result (1) shows that it increases the IRN by charge dividing, causing the DSL to be a high noise contributor; previous studies often neglected this important issue. For example, the IRN increases from 0.7 to 6.7 µV_rms [4] and from 2.8 to 4.7 µV_rms [6] when the DSL is enabled. Thus, in these cases, the DSL contributes 89.5% [4] and 40.4% [6] of the overall noise. The increased noise significantly degrades both the noise efficiency factor (NEF) [7] and the power efficiency factor (PEF) [10].

Several methods have been proposed to improve the DSL. In [5], a digitally-assisted foreground calibration is used to allow the DSL to handle residual offset. In [7], a dual DSL which consists of coarse and fine DSLs reduces the value of C_hp from 670 to 100 fF. In [8], the output of a DSL is connected to the cascode branch of a transconductor to mitigate the charge dividing effect. Nevertheless, these CCIAs consume 3.48 µW [7] and 2.13 µW [8], which results in relatively high PEFs of 18.3 and 10.5 (over a 10-kHz bandwidth), respectively. The results indicate that previous work suffers from high noise contribution from the DSL and achieves a relatively low noise-power efficiency.

In this paper, we investigate two design techniques to realize a 0.6-μW chopper amplifier with a PEF of 11.4 over a 200-Hz bandwidth. The first technique optimizes noise performance using a squeezed-inverter (SQI) stage. Because the SQI stage allows for the reduction of the supply voltage to a saturation limit of 2V_DSAT, its bias current can be increased to reduce noise. The second technique is to reduce the relatively high noise from the DSL. Unlike conventional DSLs, which are connected to the input of the CCIA through C_hp, we apply the output of the DSL to the body of a transconductor. The proposed approach not only removes the charge dividing effect but also reduces the noise by the transconductance ratio and the open-loop gain. Furthermore, this approach solves the problem of interfacing the DSL to the SQI stage, which has a different supply voltage. Using this approach, the noise contribution of the DSL is reduced to 12.5%. The fabricated CCIA achieves a relatively low noise density of 88 nV/rtHz with an integrated noise of 1.5 μV_rms. The result corresponds to a favorable NEF of 5.9 and a PEF of 11.4 by consuming only 0.68 μW, demonstrating a power-efficient low-noise amplifier.

2. Design

Figure 1 shows the schematic of the proposed CCIA. The input transconductor G_m1 is realized using an SQI stage biased at V_DD,L = 0.2 V. The transconductors G_m2, G_m3, and G_m4 are folded-cascode, two-stage opamp, and common source stages biased at V_DD,H = 0.8 V, respectively. Transconductor G_m3 is used as the integrator in the DSL. We consider the input offset voltages V_OS_i (i = 1 to 3) for G_m_i. The input V_in is up-modulated to chopping frequency f_CH by the chopper CH_in, then down-modulated to baseband by CH_out. The common-mode (CM) voltage V_CM2 = V_DD,H/2, which bypasses the chopper CH_out, is used to bias G_m2 through pseudo-resistors R_b1,2. A Miller capacitor C_m1,2 is used for stability. The mid-band gain of the CCIA is defined by input capacitor C_in1,2 and feedback capacitor C_fb1.2. The current consumptions of G_m1, G_m2, G_m3, and G_m4 are 1.61 µA, 60 nA, 210 nA, and 80 nA, respectively.

Although the SQI stage provides low noise operation, interfacing it with the DSL poses a challenge. This is because the input range of the SQI stage is limited by V_DD,L = 0.2 V, while the DSL senses the output V_out with a wide swing. We believe that this is one reason why previous studies do not implement a DSL [10]. To solve this problem, we modify the conventional DSL by connecting the output V_O,DSL of the DSL to G_m2 using the body terminal. We note that this approach is different from the previous approach wherein the output of the DSL is connected to the virtual ground node of the input transconductor through C_hp [3,4,6]. The proposed approach offers several advantages: (1) because the proposed DSL uses G_m2 instead of C_hp, the charge dividing effect is removed and noise from the DSL is reduced, (2) the noise from DSL is further reduced by the open-loop voltage gain A_V1 of G_m1 as well as by the square of the transconductance ratio, and (3) by rejecting both V_EOS and V_OS2, output offset is suppressed.

Figure 2 shows the simplified model of the proposed CCIA. Offset voltage V_OS1 creates an output ripple due to finite amplifier bandwidth. The amplitude of the output ripple can be expressed as V_out_,_r_ipple = (V_OS1A_V1G_m2)/(2C_m1,2f_CH) [4]. To suppress this ripple, we use capacitors C_b1,2 in front of CH_out. Because V_OS1 is blocked by C_b1,2, the residual ripple appearing at f_CH can be neglected. Both V_OS2 and V_EOS create output offset V_out,OS at the output. The rejection of V_EOS and V_OS2 is explained as follows: When V_EOS is up-modulated to f_CH, it is partially suppressed by C_fb1,2 at the virtual input node of G_m1. The residual offset V_EOS,ω existing at f_CH can be expressed as V_EOS,ω = V_EOS C_in1,2/(A_VC_fb1.2), where A_V is the overall open-loop voltage gain of the amplifier. This residual offset is amplified by A_V1. Simulation results show that A_V1 is 29 dB with a low-pass corner of 954 kHz. Additionally, a high-pass corner frequency of 1 Hz is created by C_in1,2 and bias resistor R_1,2 inside G_m1 (See Figure 3). Then, V_EOS,ω is down-converted by CH_out to create an offset voltage V_EOS,Gm2 = A_V1V_EOS,ω at the input of G_m2. We observe the sum of offset voltages, V_OS2,tot = V_OS2 + V_EOS,Gm2, at the input of G_m2. Transconductors G_m2 and G_m4 have a low-pass characteristic with a 3-dB frequency of about 10 Hz, and V_OS2,tot generates offset current I_O,Gm2 at the output of G_m2. The offset current is integrated by G_m4, which creates the output offset V_out,OS. This is sensed by the DSL, then V_O,DSL is applied to the body of the differential pair of G_m2. The generated current I_O,DSL = G_mb2V_O,DSL compensates I_O,Gm2. The DSL continues integrating, and V_out,OS is suppressed by the amount 1/LG(s), where the loop gain LG can be expressed as LG(s) = g_mb1,2/(s²C_m1,2R_DSL1,2 C_DSL1,2).

The selection of f_CH involves considering the various tradeoff between input impedance, output ripple, and residual offset. V_out_,_r_ipple can be reduced by increasing f_CH. One drawback of increasing f_CH is that it reduces the input impedance Z_i_n. Besides, there is greater charge injection and clock feed-through during the switching of the chopper [13]. To determine suitable f_CH, we perform periodic steady-state (PSS) and periodic noise analysis (PNOISE) simulations. Considering the tradeoff and the amplifier bandwidth, we select f_CH = 10 kHz.

3. Circuit Implementation

Figure 3a shows a schematic of the G_m1 implemented using an SQI stage [10] modified to improve the common-mode rejection ratio (CMRR). The transistors in the SQI stage are biased in the subthreshold region using V_DD,L = 0.2 V. The IRN of the G_m1 can be expressed as

\bar{V_{n, in, Gm 1}^{2}} = \frac{8 k T}{g_{m, n} + g_{m, p}} ≅ \frac{4 k T n U_{th}}{I_{DC}}

(2)

where I_DC = 800 nA is the bias current, g_m,n and g_m,p are the transconductance of M_n1 and M_p1, respectively, U_th = 26 mV is the thermal voltage, and n = 1.5 is the subthreshold factor [9]. The SQI stage reduces the noise by increasing I_DC. Because the supply voltage is reduced to a saturation limit of 2V_DSAT~0.2 V, both low noise and low power operation can be achieved.

To generate I_DC, bias voltages beyond supply rails are used for M_n1 and M_p1. The bias voltage for M_n1 is pushed above the supply rail by using a common-mode feedback (CMFB) loop. The bias voltage V_NEG for M_p1 is pushed below the ground by using a negative voltage generator, which is applied to the gate of M_p1 through a pseudo-resistor R_3,4. Because the transistors work in the subthreshold region without a tail current source, balancing the bias current for the input pair is challenging. To address this, we use a shared CMFB loop. Figure 3b shows the schematic of the CMFB circuit for the SQI stage. It monitors the CM voltage of outputs V_1,ON and V_1,OP. Then, the output V_CMFB1 of the CMFB circuit is applied to the gate of M_n1,,2 through pseudo-resistors R_1,2. Because any change in V_CMFB1 affects the input pair by the same amount, this approach provides balanced bias currents for the SQI stage.

Figure 4a shows the schematic of the negative voltage generator. It consists of a 1/10-scaled current replica, two switched-capacitor (SC) paths, a level shifter, and a folded-cascode (FC) amplifier. The SC network consists of the main path and a low noise replica. The FC amplifier and the main SC path generate the bias voltage V_G for M_1B by regulating V_D to V_DD,L/2. The replica path is responsible for copying V_G to generate V_NEG. The current mirror defines an 80 nA through M_1B, which is the 1/10-scaled current of M_p1,2. The negative voltage generator draws 18 nA from V_DD,H and 80 nA from V_DD,L. Figure 4b shows the statistical distribution of V_NEG obtained from Monte Carlo simulations. The result shows an average value of −177.3 mV with a standard deviation of 12.4 mV.

Figure 5a,b shows the statistical distributions of the bias current and the output CM voltage obtained from 200 Monte Carlo simulations. Both random mismatch and process variations are considered. The result shows an average bias current of 766 nA with a standard deviation of 62 nA. The output CM voltage shows an average value of 98.3 mV with a standard deviation of 3.4 mV. Compared to previous work which uses two separate CMFB loops [10], the proposed approach increases the CMRR from 85 to 105 dB. This indicates that the proposed shared CMFB loop is effective in improving CMRR. Figure 5c shows the gain of the SQI stage depending on temperatures as a function of V_DD,L. Because the transistors are biased in the subthreshold region, the increased threshold voltage with temperature reduces the gain [10]. We note that the SQI stage still provides a gain >20 dB when V_DD,L is reduced to 0.15 V at 70 °C. At room temperature, the SQI stage achieves a gain of 29 dB with V_DD,L = 0.2 V.

Figure 6 shows a schematic of G_m2 with the body-controlled DSL. The bias current of G_m2 is 40 nA. The CMFB circuit (not shown) generates the output V_CMFB2 using a 20 nA bias current (See Table 1 for the power consumed by the CMFB circuits). The overall current of G_m2 is only 60 nA. Figure 7a shows a schematic of the DSL. The R_DSL1,2 and C_DSL1,2 are the resistors and capacitors in the DSL, respectively. R_DSL1,2 is a variable pseudo-resistor controlled by V_PR, which is realized by cascading floating PMOS transistors. The input of G_m3 is associated with offset V_OS3. Voltage V_OS3 can disturb V_out of the CCIA similarly to other offsets (V_OS1, V_OS2, V_EOS,Gm2). To reduce the effect of V_OS3, two choppers, CH_D1 and CH_D2, are added to the integrator. Because the bandwidth of the integrator is relatively narrow (~30 mHz), V_OS3 is up-modulated to the outside of the integrator’s bandwidth by CH_D2. Figure 7b shows a schematic of the two-stage opamp for G_m3. The first stage is biased using 5 nA. The second stage is biased at 200 nA for enhanced swing. The CMFB circuit generates V_CMFB3 using a 5 nA bias current. The overall current is 210 nA.

The transfer function of the DSL has a low-pass characteristic for V_out. It can be expressed as −g_mb1,2/(sR_DSL1,2C_DSL1,2), where g_mb1,2 is the body transconductance integrated into G_m2. Within the feedback loop, the DSL creates a high-pass corner to reject V_EOS. Using the condition C_fb1,2 << C_in1,2, the transfer function of the CCIA can be expressed as

H (s) ≅ - \frac{A_{V 1} g_{m 1, 2}}{C_{m 1, 2}} \frac{s}{(s + η ω_{ugb} / β A_{V 1}) (s + β A_{V 1} g_{m 1, 2} / C_{m 1, 2})}

(3)

where g_m_1,2 is the transconductance of the input pair of the G_m2, η = (g_mb1,2/g_m1,2) ≈ 0.25, ω_ugb = 2πf_ugb = 1/(R_DSL1,2C_DSL1,2) is the unity-gain frequency of the integrator, and β = C_fb1,2/C_in1,2 is the feedback factor. Using (2), we obtain a high-pass corner frequency f_hp = (η/βA_V₁) f_ugb.

Because f_hp created by the DSL depends on the value of pseudo-resistor, we investigate the variability of R_DSL1,2. Figure 8a shows the value of the R_DSL1,2 as a function of temperature for various V_PR. The resistance increases with V_PR while it decreases with temperature. Figure 8b shows the statistical distribution of the resistance obtained from Monte Carlo simulations at 27 °C and V_PR = 0.4 V. The result shows that the average value of R_DSL1,2 is 34.1 GΩ with a standard deviation of 1.6 GΩ. Figure 9 shows a schematic of the bias generator. It consists of a constant-g_m current reference and six branches to generate the bias voltages for the amplifier. Overall current consumption is 47.5 nA.

The proposed CCIA uses a narrow margin for the stacked transistors in the SQI stage. Therefore, we investigate the effect of supply and temperature on the performance of the amplifier. Figure 10 shows the effect of V_DD,L on the bias current (SQI stage only), noise, and bandwidth. When V_DD,L is increased, it is tracked by V_D and V_G in the negative generator, which increases V_NEG to keep the bias current. When V_DD,L is reduced below 0.15 V, the two stacked transistors are driven in the deep subthreshold region, which reduces the current and the gain. We note that the CCIA still operates with an integrated noise < 1.5 μV_rms when V_DD,L is reduced to 0.15 V. The amplifier bandwidth gradually increases with V_DD,L, which agrees with the previous result [10].

Because V_DD,L is relatively low, an external electromagnetic interference can affect the sensor interface. In the proposed CCIA, the differential input signal V_IN is up-modulated to f_CH while the CM signal is not chopped. Therefore, chopping provides some means of rejection of external interference. In the case when the external interference exists at around f_CH, it can affect the CCIA, however, this is well beyond the amplifier bandwidth (1–200 Hz). When the CCIA is used for the sensor readout, a theoretical input range calculated using a gain of 40 dB and the maximum output swing of 0.8 V_pp is 8 mV_pp, which agrees with the measured value of 6 mV. Because the input is capacitively-coupled, it provides a relatively high DC blocking allowed by the voltage rating of C_in_1,2.

Figure 11 shows the effect of temperature on the amplifier. The bias current increases with the temperature as expected from the constant-g_m current reference, which increases V_NEG. The two temperature-dependent parameters of the subthreshold current are mobility and the threshold voltage [14]. The increased threshold voltage with temperature reduces the gain A_v. The bandwidth can be expressed as BW = ω_p(1+βA_v), where ω_p is the 3-dB frequency and β is the feedback factor. Furthermore, the increased temperature reduces the bandwidth [15,16]. The amplifier achieves an integrated noise of less than 2 µV_rms over the temperature range from −5 °C to 45 °C.

The IRN of the CCIA,

\bar{V_{n, i n}^{2}}

, can be expressed as

\begin{array}{l} \bar{V_{n, in}^{2}} = {(\frac{C_{tot}}{C_{in 1, 2}})}^{2} [\bar{V_{n, in, Gm 1}^{2}} + \frac{1}{A_{V 1}} \{\bar{V_{n, in, Gm 2}^{2}} + \bar{V_{n, out, DSL}^{2}} {(\frac{g_{mb 1, 2}}{g_{m 1, 2}})}^{2}\}] \\ = {(\frac{C_{tot}}{C_{in 1, 2}})}^{2} [\frac{4 k T n U_{th}}{I_{DC}} + \frac{8 k T n}{A_{V 1} g_{m 1, 2}} (1 + \frac{g_{m 3, 4} + g_{m 9, 10}}{g_{m 1, 2}}) + \frac{2}{A_{V 1}} {(\frac{g_{mb 1, 2}}{g_{m 1, 2}})}^{2} \{(8 k T n R_{DSL 1, 2} + \bar{V_{n, in, OTA}^{2}}) {(\frac{1}{s R_{DSL 1, 2} C_{DSL 1, 2}})}^{2}\}] \end{array}

(4)

where C_tot = C_in1,2 + C_fb1,2 + C_p,

\bar{V_{n, in, Gm 1}^{2}}

and

\bar{V_{n, in, Gm 2}^{2}}

are the input-referred noise of G_m1 and G_m2, respectively,

\bar{V_{n, out, DSL}^{2}}

is the output-referred noise of the DSL, and g_mi represents the transconductance of the transistors in G_m2. The noise from the DSL includes the thermal noise of R_DSL1,2 and the noise

\bar{V_{n, in, OTA}^{2}}

= 1.8 nV/√Hz of the two-stage opamp. We note that

\bar{V_{n, out, DSL}^{2}}

is not only multiplied by (g_mb1,2/g_m1,2)² << 1, but is also reduced by A_V1 = 29 dB. Using the values g_m1,2 = 0.7 µS, g_m3,4 = 0.35 µS, g_m9,10 = 0.7 µS, C_in1,2 = 4 pF, C_fb1,2 = 40 fF, and C_p = 66.5 fF, we obtain

\bar{V_{n, i n}^{2}}

= 84.2 nV/√Hz. Using the shot noise model [10], we obtain a similar value for

\bar{V_{n, i n}^{2}}

. Over the signal bandwidth of 200 Hz, the integrated noise contributions from G_m1, G_m2, DSL, and the other blocks are 44.9%, 39.1%, 12.5%, and 3.5%, respectively.

4. Measured Results

Figure 12 shows a microphotograph of the CCIA fabricated using a 180-nm CMOS process. The core area is 0.19 mm². The supply voltages V_DD,L and V_DD,H are generated using external power supplies. Figure 13 shows the measured frequency response of the CCIA. The result shows a mid-band gain of 40 dB with a 3-dB bandwidth of 800 Hz. The high-pass corner f_hp was successfully created using the proposed DSL and varies from 0.36 to 2.4 Hz when V_PR is changed from 0.68 to 0.35 V. Figure 14 shows that the measured low-frequency CMRR > 105 dB. The power supply rejection ratios (PSRRs) measured at V_DD,L and V_DD,H show that low-frequency PSRR_L > 80 dB and PSRR_H > 75 dB, respectively.

Figure 15 shows the measured noise spectral density. The input-referred noise density is 88 nV/rtHz, which is slightly higher than the calculated value of 84.2 nV/rtHz. When the DSL is enabled, the noise integrated from 1 to 200 Hz increases from 1.3 to 1.5 μV_rms. We note that the noise contribution from the DSL is just 12.5%, which is much lower than the previous results of 89.5% [4] and 40.4% [6]. Figure 16 shows the measured output of the CCIA for prerecorded human EEG (~100 μV) and ECG (~1 mV) input signals [17]. Table 1 shows the power breakdown of the proposed CCIA.

Table 2 shows a performance comparison with the state of the art. The tradeoff between the noise and power can be evaluated using PEF as

PEF = V_{ni, rms}^{2} \frac{2 P_{DC}}{π U_{th} 4 k T \cdot B W} = {NEF}^{2} \cdot V_{DD}

(5)

where V_ni,rms is the input-referred root-mean-square (rms) noise voltage, P_DC is the power consumption, and BW is the amplifier bandwidth. The previous approaches [4,7,12] use relatively-high currents to reduce noise. Because a high supply voltage V_DD > 1 V is used except for in [6], the large power consumption >1.8 µW leads to a relatively high PEF. By using the SQI stage with an ultra-low voltage, the proposed CCIA achieves a competitive noise performance of 1.5 μV_rms at a relatively low power of 0.61 µW (0.68 µW including bias generators). Our work achieves a good PEF of 10.2 (11.4 with bias generators) which is the lowest of the work shown in Table 2. Besides, the proposed CCIA has the lowest noise contribution of 12.5% from the DSL. The work in [10] achieves a good NEF/PEF = 2.1/1.6, however, their design does not include a DSL. Therefore, direct comparison is difficult. Although the dual power approach requires additional buck converter, a high-efficiency (>80%) converter consuming sub-nW can be used for voltage step-down [18,19].

5. Conclusions

In this paper, we investigated a sub-μW chopper amplifier using a noise-efficient DSL and power-efficient SQI stage. The proposed DSL not only removes the charge dividing effect but also reduces noise caused by both the transconductance ratio and the open-loop gain. Using the proposed approach, the noise contribution from the DSL is reduced to below 12.5%, which is much lower than the value seen in previous work. For power efficiency, we use an SQI stage biased by a supply voltage reduced to the 2V_DSAT saturation limit. The challenge of biasing the SQI stage and interfacing with a DSL having a different supply domain is addressed. Measurement of the fabricated CCIA shows an IRN of 1.5 μV_rms with the DSL enabled. The noise density is 88 nV/rtHz at a 40 dB gain when consuming 0.6 µW. The PEF is 11.4, which compares favorably with the state of the art.

Author Contributions

X.T.P. designed the circuit, performed the experimental work, and wrote the manuscript. N.T.N. performed noise analysis and revised the manuscript. V.T.N. performed circuit simulations and revised the manuscript. J.-W.L. conceived the project, organized the paper content, and edited the manuscript. All authors have read and agreed to the published version of the manuscript.

Funding

This research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF-2018R1A2A2A05018621).

Acknowledgments

The chip fabrication and CAD tools were made available through the IDEC (IC Design Education Center).

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Schematic of the proposed capacitively-coupled chopper instrumentation amplifier (CCIA) using body-controlled DC servo loop (DSL). C_in1,2 = 4 pF, C_fb1,2 = 40 fF, C_b1,2 = 3 pF, C_m1,2 = 4 pF, R_m1,2 = 4 MΩ, and C_DSL1,2 = 5 pF.

Figure 2. A simplified model of the proposed CCIA.

Figure 3. (a) Schematic of the squeezed-inverter stage using the shared common-mode feedback (CMFB). V_CM1 = 0.1 V, V_NEG = −0.18 V, and V_CMFB1 = 0.098 V (nominal value). (b) Schematic of the proposed CMFB circuit. V_B01 = 0.57 V, V_B11 = 0.28 V, V_B21 = 0.49 V, and V_B31 = 0.23 V.

Figure 4. (a) Schematic of the negative voltage generator, (b) statistical distribution of V_NEG.

Figure 5. Monte Carlo simulation results for the (a) bias current, (b) output common-mode (CM) voltage of the squeezed-inverter (SQI) stage. (c) simulated gain of the SQI stage depending on V_DD,L and temperature.

Figure 6. Schematic of transconductor G_m2 with body-controlled DSL. C_M3,4 = 0.5 pF. V_B02 = V_B12 = 0.52 V, V_B22 = 0.18 V, V_B23 = 0.6 V, and V_CMFB2 = 0.28 V (nominal value).

Figure 7. (a) schematic of the DSL and (b) schematic of the two-stage opamp G_m3. C_DSL1,2 = 5 pF, C_C1,2 = 0.5 pF. V_B03 = 0.57 V, V_B13 = 0.34 V, and V_CMFB3 = 0.29 V (nominal value).

Figure 8. (a) simulated value of the pseudo-resistor as a function of temperature for various V_PR and (b) Monte Carlo simulation result of the pseudo resistor value at V_PR = 0.4 V.

Figure 9. Schematic of the bias generator.

Figure 10. Simulated results showing the effect of V_DD,L on the noise and bandwidth of the proposed CCIA.

Figure 11. Simulated bias current, noise, and bandwidth depending on temperature.

Figure 12. Chip microphotograph of the proposed CCIA.

Figure 13. The measured frequency response.

Figure 14. Measured CMRR and power supply rejection ratio (PSRR) as a function of frequency.

Figure 15. Measured input-referred noise voltage spectral density.

Figure 16. Measured output of the CCIA.

Table 1. Power breakdown.

Block	Components	Current (nA)	Voltage (V)
G_m1 (SQI stage)	Input pair	1600	0.2
G_m1 (SQI stage)	CMFB	10	0.8
G_m2 (Folded-cascode)	Input pair	20	0.8
G_m2 (Folded-cascode)	Cascode branch + CMFB	40	0.8
G_m3 (Two-stage opamp)	Input pair	5	0.8
G_m3 (Two-stage opamp)	Common source + CMFB	205	0.8
G_m4 (Common-source)	Input pair	80	0.8
Bias circuits	Current mirror	80	0.2
Bias circuits	Bias generators	65.5	0.8
Total power	676.4 nW

Table 2. Performance summary and comparison.

	[3]	[4]	[6]	[7]	[12]	This Work
Power (µW)	2.0	1.8	0.6	3.48	2.8	0.61/0.68 ^†
Supply (V)	1.8	1.0	0.5	1.2	1.2	0.2/0.8
Current (µA)	1.1	1.8	1.2	2.9	2.3	1.6/0.36 1.68 ^†/0.43 ^†
Input cap. (pF)	15	12	12	20	1.0	4
Gain (dB)	41	40	40	40	25.7	40
CMRR (dB)	100	134	106	85	78	105
Noise (µV_rms)	1.0	6.7	4.7	N/A	1.8	1.5
Noise floor (nV/rtHz)	100	60	140	47	80	88
Bandwidth (Hz)	100	100	250	N/A	200	200
DSL noise contribution (%)	N/A	89.5	40.4	26	N/A	12.5
NEF /PEF	5.4/52.5	37.4/1398	7.5/27.9	3.9/18.3	7.4/66.4	5.7/10.2 5.9 ^†/11.4 ^†
Tech. (nm)	800	65	180	130	40	180
Area (mm²)	1.7	0.3	1.0	0.3	0.07	0.19

* Including DSL, ^† Including bias circuits. When the additional power (84 nW) of an 80% efficient buck converter is included, NEF/PEF increases to 6.5/12.6.

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Pham, X.T.; Nguyen, N.T.; Nguyen, V.T.; Lee, J.-W. A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing. Sensors 2020, 20, 2059. https://doi.org/10.3390/s20072059

AMA Style

Pham XT, Nguyen NT, Nguyen VT, Lee J-W. A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing. Sensors. 2020; 20(7):2059. https://doi.org/10.3390/s20072059

Chicago/Turabian Style

Pham, Xuan Thanh, Ngoc Tan Nguyen, Van Truong Nguyen, and Jong-Wook Lee. 2020. "A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing" Sensors 20, no. 7: 2059. https://doi.org/10.3390/s20072059

APA Style

Pham, X. T., Nguyen, N. T., Nguyen, V. T., & Lee, J.-W. (2020). A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing. Sensors, 20(7), 2059. https://doi.org/10.3390/s20072059

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A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing

Abstract

1. Introduction

2. Design

3. Circuit Implementation

4. Measured Results

5. Conclusions

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