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Principles of VLSI Design CMPE 413

Interconnect and Wire Engineering
Interconnect
Analysis of interconnect is becoming as important as transistors in modern processes.
Modern processes use 6-10 metal layers
Layer stack for 180nm process
Pitch = w + s
Aspect Ratio = t / w
Newer processes have AR ~ 2
Thicker wires as you move towards
upper metal layers
Layer T (nm) W (nm) S (nm) AR
6 1720 860 860 2.0
1000
5 1600 800 800 2.0
1000
4 1080 540 540 2.0
700
3 700 320 320 2.2
700
2 700 320 320 2.2
700
1 480 250 250 1.9
800
Substrate
l
w s
t
h
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Wire Resistance
l
w
t
1 Rectangular Block
R =R (L/W)
4 Rectangular Blocks
R =R (2L/2W)
=R (L/W)
t
l
w w
l
resistivity m ( ) =
R

t
---
l
w
---- R
l
w
---- = =
R =
sheet resistance
( )
Count number of squares and multiply by sheet resistance to get R
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Wire Resistance
Older processes used aluminum, today's processes use copper
Special barrier layer required to stop copper from diffusing into silicon and destroying
transistors
Typical sheet resistance values in 180nm process
Layer Sheet Resistance
Diffusion (silicided) 3-10
Diffusion (unsilicided) 50-200
Polysilicon (silicided) 3-10
Polysilicon (unsilicided) 50-400
Metal1 0.08
Metal2 0.05
Metal3 0.05
Metal4 0.03
Metal5 0.02
Metal6 0.02
( )
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Contact Resistance
Contacts and vias also have about 2-20 of resistance.
Higher resistance than that of metal wires.
Use many contacts to get lower R
As current crowds at the periphery, many small contacts required rather than one huge
contact.

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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Wire Capacitance
Wire have capacitance per unit length to neighboring layers and layers above and below
C
total
= C
bottom
+ C
top
+ 2C
adjacent
Parallel plate capacitance equation
Wires are not truly parallel plate, but obey trends
Increasing area (W or t) increases capacitance
Increasing distance (s or h) decreases capacitance
layer n+1
layer n
layer n-1
C
adj
C
top
C
bot
w s
t
h
1
h
2
C A d =
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Wire Capacitance
Dielectric constant in the previous equation

0
= 8.85 x 10
-14
F/cm and k = 3.9 for SiO
2
Newer processes are starting to use low-k dielectric materials to reduce capacitance
k
0
=
0
50
100
150
200
250
300
350
400
0 500 1000 1500 2000
C
t
o
t
a
l

(
a
F
/

m
)
w (nm)
Isolated
M1, M3 planes
s =320
s =480
s =640
s=
8
s =320
s =480
s =640
s=
8
Typically wire have ~0.2fF/m
Gate capacitance ~2fF/m
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Diffusion and Polysilicon Capacitance
Diffusion capacitance is very high (~2fF/m)
Comparable to gate capacitance
Diffusion also has high resistance
Avoid using diffusion runners for wires!!
Polysilicon has lower C but higher R
Use for transistor gates
Occasionally for very small wires between gates
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Wire Delay: Lumped Element Models
Wires are a distributed system
Approximated using lumped element models
3 segment -model is accurate to within 3% in simulations
L-model would require about 100 segments to obtain the same accuracy
Use single segment -model for Elmore delay
C
R
C/N
R/N
C/N
R/N
C/N
R/N
C/N
R/N
R
C
L-model
R
C/2 C/2
R/2 R/2
C
N segments
-model T-model
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Wire Delay: Lumped Element Models
Example: Metal2 wire in 180nm process that is 5 mm long and 0.32 m wide
Construct a 3 segment -model
and
Estimate delay of 10x inverter driving a 2x inverter at the end of the above wire
for gates
Unit inverter: 0.36 m for NMOS, 0.72 m for PMOS
R 0.05 = R 781 = C
permicron
0.2fF m C 1pF = =
260
167 fF 167 fF
260
167 fF 167 fF
260
167 fF 167 fF
R 2.5k m =
781
500 fF 500 fF
Driver Wire
4 fF
Load
690
t
pd
= 1.1 ns
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Crosstalk
A capacitor does not like to change its voltage instantaneously
A wire has high capacitance to its neighbor
When neighbor switches from 1-> 0 or 0 -> 1 the wire tends to switch too
Called capacitive coupling or crosstalk
Effects: Noise on non-switching wires and increased delay on switching wires
Assume wires above and below on average are quiet and there-
for second terminal of capacitor can be ignored
Modeled as C
gnd
= C
top
+ C
bottom
Effective C
adjacent
depends on behavior of neighbors
Miller Effect (Miller Coupling Factor MCF)
B DV
C
eff(A)
MCF
constant V
DD
C
gnd
+ C
adjacent
1
switching same direction as A 0 C
gnd
0
switching opposite direction as A 2V
DD
C
gnd
+ 2C
adjacent
2
A B
C
adj
C
gnd
C
gnd
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Crosstalk
Crosstalk causes noise on non-switching wires
If the victim is floating
model as capacitive voltage divider
C
adj
C
gnd-v
Aggressor
Victim
V
aggressor
V
victim
V
victim
C
adj
C
gnd v
C
adj
+
--------------------------------------V
aggressor
=
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Crosstalk Noise: Victim
Usually victim is driven by a gate that fights noise
Noise depends on relative resistances
Victim driver is in linear region, aggressor in saturation
If sizes are same, R
aggresor
= 2-4 x R
victim
C
adj
C
gnd-v
Aggressor
Victim
V
aggressor
V
victim
R
aggressor
R
victim
C
gnd-a
V
victim
C
adj
C
gnd
v C
adj
+
---------------------------------------
1
1 k +
------------V
aggressor
=
k

aggressor

victim
-------------------------
R
aggressor
C
gnd a
C
adj
+ ( )
R
victim
C
gnd v
C
adj
+ ( )
----------------------------------------------------------------------- = =
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Crosstalk Coupling: Waveforms
Simulated coupling for C
adj
= C
victim
Aggressor
Victim (undriven): 50%
Victim (half size driver): 16%
Victim (equal size driver): 8%
Victim (double size driver): 4%
t (ps)
0 200 400 600 800 1000 1200 1400 1800 2000
0
0.3
0.6
0.9
1.2
1.5
1.8
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Crosstalk noise
Noise implications:
If the noise is less than the noise margin nothing happens
Static CMOS logic will eventually settle to correct output even if disturbed by a large
noise spike
But these glitches cause extra delay
Also causes extra power from false transitions
Dynamic logic (discussed later) will never recover from noise
Memories and other sensitive circuits can also produce wrong answers
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Wire Engineering
Goal: Achieve delay, area and power specifications with acceptable noise
Degrees of freedom
Width, Spacing, Layer and Shielding
D
e
l
a
y
(
n
s
)
:
R
C
/
2
Wire Spacing
(nm)
C
o
u
p
l
i
n
g
:
2
C
a
d
j
/

(
2
C
a
d
j +
C
g
n
d
)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 500 1000 1500 2000
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 500 1000 1500 2000
320
480
640
Pitch (nm)
Pitch (nm)
vdd a
0
a
1
gnd a
2
vdd b
0
a
1
a
2
b
2
vdd a
0
a
1
gnd a
2
a
3
vdd gnd a
0
b
1
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Repeaters
R and C are proportional to l
RC delay is proportional to l
2
Unacceptably high for long wires
Break long wires into N shorter segments
Drive each segment with an inverter or buffer
Wire Length: l
Driver Receiver
l/N
Driver
Segment
Repeater
l/N
Repeater
l/N
Receiver Repeater
N Segments
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Repeaters
How many repeaters should we use?
How large should each one be?
Equivalent circuit
Wire length l
Wire capacitance C
w
* l, Resistance R
w
* l
Inverter width W (NMOS = W, PMOS = 2W)
Gate capacitance C`* W, Resistance R / W
R/W
C'W C
w
l/2N C
w
l/2N
R
w
lN
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Principles of VLSI Design CMPE 413
Interconnect and Wire Engineering
Repeaters
Write equation for Elmore Delay
Differentiate with respect to W and N
Set equal to 0 and solve
l
N
----
2RC'
R
w
C
w
--------------- =
W
RC
w
R
w
C'
------------- =
t
pd
l
------- 2 2 + ( ) RC'R
w
C
w
=
Best length of wire between repeaters, neglecting diffusion parasitics
NMOS transistor width to achieve this delay
Delay per unit length of a properly repeated wire is