EDA Introduction

Professor: Sci.D., Prof. Vazgen

Melikyan

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Course Overview

 Introduction
 1 lecture
 IC Design Data Formats and Tools
 4 lectures
 Electronic Design Methodology
 4 lectures
 IC Synthesis
 2 lectures
 Databases for EDA
 3 lectures
 IC Design Approaches and Flows
 3 lectures
 EDA Tools
 3 lectures
 Overview of Synopsys EDA Tools
 3 lectures

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EDA Tools

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Requirements to EDA Software

 Efficiency (for performance and memory consumption)

 Ease of use (application of simple problem-oriented languages)
 Availability of errors diagnostic tools of user
 Reliability and accuracy of getting design results
 Universality with respect to certain constraints of solving tasks
 Openness (adaptability) for changes in service programs
 Maintainability, characterizing performance of programs when
making changes in them
 Mobility in restructuring programs from computers of one type to
another.

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System Software

Integration Control of project

tools integrity

Product Data
Management Implementation of
Model project operations
generation

Library control Data

transformation

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Structure of the System Software

System Software

Operating System Library of standard programs

(OS) DBMS

Solution of general
mathematical problems

 Control of calculation process

 Storing, searching, sorting,
 Input, output and partial processing of
modification of data needed for
information
design
 Dialog Interaction with the user in the
 Protection of integrity and
design process
protection from unauthorized
 Control and diagnostics of work of
access
computer system

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Structure of Operating System

 Operating systems include:

 Processing programs comprising subsystem of preparing a program of
the user (external software)
 Controling software, forming a group of executing programs of the user
(internal software)
Operating System

Processing program Control program

Translators Serving Supervisor Data Control

Programs
Control with tasks
Libraries

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Application Software

Synthesis Physical Design

Tools Tools

EDA Tools
Circuit Design
Verification
Tools Tools

Testing Other Special

Tools Tools

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Principles of Organizing Application
Software
 The software should be developed on the basis of:
 Modularity
 Hierarchy
 Principles of modularity and hierarchy allow organizing collective
parallel development of various parts of software, creating open
software systems, facilitating their comprehensive debugging and
information coordination.
 System level processing of applied software, level of applied
programs and level of subprograms (modules) are distinguished.
 Connection between separate software modules can be
implemented by control, information, placement and impact.

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EDA Tool Flows

 A tool flow describes the method and order (the methodology) in

tools used to produce a design
 Different companies can take the same toolset and use a different methodology to
produce an IC
 Typically, companies add their own in-house tools to off-the-shelf tools to tailor
the tool flow to their particular needs
 An EDA group is usually responsible for designing and maintaining the
methodology – also responsible for training others in the use of this methodology.

IC design companies

EDA Set Design

toolset of tools In-house tools
methodology

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 EDA Tool Flows (2)

Design Implementation Tools Design Levels Design Verification Tools

System Simulators
System Level Behavioral HDL
Design
HDL Simulators

Code Coverage
RTL
RTLSynthesis Gate Level
Simulators

Static Timing
Analysis
Logic Synthesis and Gate-Level
Mapping Hardware
Accelerators

Design Rules Check

Physical Synthesis Physical (DRC),Layout vs.
Domain Schematic (LVS)

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EDA and Testing Tools

Behavioral

RTL

Testbench Simulation
Gate Level
(post-synthesis,
pre-layout)

Gate Level
Goal is to use the same testbench for all levels of
(post-synthesis,
simulation abstraction, and mix different levels post-layout)

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Capabilities of EDA Tools

 Manual layout vs. EDA is like:

 Manual transmission vs. automatic transmission
 HTML programming vs. frontpage
 Assembly code programming vs. compiled high-level language

 Manual layout for small, optimized designs will always be superior

 EDA techniques for larger-scale designs will always be superior

(verification, reusability, etc.)

 Goal: do careful, manual design of smaller components (cells) and

use EDA to combine them for large-scale design

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 Capabilities of EDA Tools (2)

process information,
 Design Flow cell abstracts
Abstract Generation
Circuit Simulation

characterization
Digital cell library
Characterization information
design

Design
Specification Standard Cell Library

Behavioral VHDL Design Synthesis

Place and Route
VHDL Verilog

Behavioral Simulation Cell Timing Simulation Interconnect Timing

Simulation

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Tools and Design Methodology

Architecture Tools  Tools and design

System System Level
Tools
methodology
Level are inextricably
RTL
RTL Level
Tools
interwoven-like an
“Electronic” DNA
Gate Logic Synthesis
Level
Tools  Underlying architecture
adds yet another
Transistor Transistor Level
Level
Tools dimension.
Physical Physical Synthesis
Tools
Level

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History of EDA Tools: First
Generation
 EDA was introduced in the 1970s.

 Most of the work including layout was manual; polygons were cut
out for mask making.

 Berkeley Spice was introduced in 1975; laid the foundation for EDA
tools - easier optimization; boost in efficiency for user.

 Polygon data for layouts was entered into computers / Design rule
checks still a burden of the user.

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History of EDA Tools: First
Generation (2)
 With simulation, design errors were brought down but the transfer of
data to geometric level could not be verified
 Geometric checks (DRC: Design Rule Check) were introduced
 Layout extraction (layout versus schematic check)
 Manual work was required to go down the Y chart along behavioral
axis
 The jump from Boolean equations to Gates / Flip-flops was manual
 The jump from Gates / Flip-flops to polygons was also manual
 Only verification was automated

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History of EDA Tools: Second
Generation
 Started around 1980s
 Automatic place and route was introduced
 Logic simulators came into being - circuits
have only three states (0,1,X=unknown)
 The jump from behavioral to structural to
attain a gate level netlist was manual
 All other lower level work was automated

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History of EDA Tools: Third
(Current) Generation
 Work started in universities to automate all
levels of digital design
 The term silicon compiler was introduced
 Initially good examples were demonstrated but it
was clear that human interaction is needed for
customization of final IC in practical designs
 HDL languages such as VHDL (1987) and
Verilog (1995) were introduced and
standardized
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History of EDA Tools: Third
(Current) Generation (2)
 Synopsys introduced Design Compiler which is a
logic synthesis tool along with HDL compiler
which is for RTL synthesis
 Acceptance of these tools was slow
 Heavy price tag
 Quality was not as good as manual designs
 By early 90s automation was adopted in practice
and HDL languages were taught in universities

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Verifcation

 Formal verification
 Verify by constructing original function from synthesized circuit
(compare result from different abstraction levels)
 Static timing analysis
 Calculate the gate delays along signal path to verify timing
 The maximum and minimum delays are considered for further
analysis
 Automatic test pattern generation
 Not detached from logic synthesis
 Synthesize in a way that the circuit is testable

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Outlook on the Fourth Generation of
EDA Tools
 Design Re-use
 Core idea - multiple usage of a single design
 Re-use designs already available such as cores for
microprocessors
 Behavioral Synthesis
 Raise manual design work to higher abstraction levels
 Algorithmic description to RTL description
 Synthesis from a C language description
 Synthesis of behavioral description of RF/analog circuits

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Outlook on the Fourth Generation of
EDA Tools (2)
 Hardware-software co-design
 Design hybrid systems
 Signal integrity
 Interconnects/ EM interference
 Power supply/ ground plane analysis
 Mixed signal: mixed analog-digital simulation
 Thermal analysis: self-heating problem with
transistors

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Tour of Design Automation Tools

 Algorithmic and system design

 Structural and logic design
 Transistor-level design
 Layout design
 Verification methods
 Data management tools

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Algorithmic and System Design

 Designs generally start with specifications

 Designers translate specifications into algorithms that are coded in hardware
description languages (HDLs)
 Examples of HDLs include Verilog and VHDL
 They are different from normal programming languages as most of the code is
executed in parallel as opposed to being sequential execution
 Early Verilog compilers converted code to C language and used standard C
compilers
 Specifications using HDL are unambiguous as opposed to specifications in a natural
language like English
 Simulation of HDL code is instrumental in finding errors in specifications a well as the
description using HDL code
 Designers can get a feel for the overall performance of the system without the need
to generate any circuits

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System Level Simulation Tools

 C, C++
 SystemC, SystemVerilog
 A modeling platform supports different levels of
abstraction
 A simulation kernel
 Matlab

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Synthesis Tools

 It is possible to convert HDL specification into a gate level netlist using

synthesis tools. To do that, the HDL description has to be synthesizable.
 The level of abstractions, synthesis tools are involved with, gives an idea of
the power of the tool
 A synthesis tool that takes algorithmic specifications and produces a
structural description is a more powerful tool and this process is called
“high-level-synthesis“.
 Earlier the term silicon compiler was introduced to automate all the tasks
involved from generating masks for layout to specifications
 Synthesis tools are a practical approximation to this idea
 Few examples of vendors: Synopsys Synplicity, Xilinx, FPGA express, etc.

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Graphical Entry

 Certain standard modules need not always be written using VHDL

or Verilog as they are general with variations in specifications
 For example, finite state machines (FSM)
 Graphical entry tools are available that can take the specifications of
an FSM using diagrams
 They generate VHDL, Verilog code for the given input FSM diagram
 Many tools have included this feature
 Especially useful in case certain states are FSMs by themselves.
These are called hierarchal FSMs.

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Hardware/Software Co-Design

 Design specifications of any large systems do not lead to one chip

 It generally leads to a set of chips interconnected with each other
 Effort is to put everything on a chip (System-on-chip SOC)
 Cost prevents this approach: until then multiple chips are going to be present
 In either case, the important thing to address is which part of the system is going to
be hardware based and which part software based
 Tools are to assess which part has to be hardware based and which part software
based
 It is determined by the frequency of visit to concerned module
 Frequently visited modules are preferred to be hardware based and less frequently
visited modules - software based
 The tools have to automatically decide this and generate suitable HDL/C code
accordingly

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Structural and Logic Design

 If it is not possible (or is more complicated) to provide a high-level

description of a circuit; a schematic editor is used
 It directly deals with the structural level design
 Involves interactive specification of modules/blocks and their
interconnections
 The schematics can also be hierarchal: a block at one level is an
interconnection of blocks in another level
 Blocks at lowest level are either gates or flip-flops
 Transistor level detail is still not present
 Simulation is performed to verify results
 Test vectors and test patterns are generated from this by using tools
 Logic synthesis: generation and optimization of circuits at the level of
Boolean gates
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Logic Synthesis Tools: Examples

 Design Compiler (Synopsys)

 The most popular logic synthesizer, bottom-up and
top-down approach
 Encounter (Cadence)
 logic synthesizer, top-down approach

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Transistor-Level Design

 3 different levels of simulation

 Switch level
 Transistors are treated as switches
 Bidirectional entities as opposed to unidirectional gates
 The signals are mostly digital; but are enhanced to deal with different signal strengths
 Timing level
 Analog signals are considered
 Transistors have simple models (e.g. piecewise linear functions)
 Circuit level
 More accurate models used (e.g. bsim3 model for CMOS)
 Form nonlinear differential equations
 Solved by numerical integration
 Require more time to solve but are more accurate
 Synopsys HSPICE is the industry de-facto standard tool for
transistor level simulation
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RTL Simulation Tools: Example

 VCS (Synopsys)
 Faster when it comes to RTL simulation
 Direct C kernel interface
 Code coverage embedded
 Better integration with VERA and other Synopsys
tools.
 Incisive (Cadence)
 Multi-language simulator

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Layout Verification at Transistor
Level
 Layouts are usually verified by performing extraction
 Extraction processes patterns on the layout
 Identifies transistors, capacitors, inductors, resistors, etc.
 Generates a transistor level netlist
 Used for verifying that there are no errors in layout
 Also used to predict higher-order effects neglected
during previous design stages
 Can be verified at switch, timing or circuit levels
 Signal integrity tools: interconnects

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Physical Synthesis Tools: Example

 IC Compiler / IC Compiler II (Synopsys)

 Silicon Ensemble (Cadence)

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Layout Design

 Diverse layout tools exist

 Layout is a set of polygons
 Composition of IC layout is performed in 2 stages
 Placement: Find a position for each sub-block to minimize area that will be occupied by
interconnections
 Routing: Connect all the required blocks so that interconnections occupy minimum area
 Minimize the chip area while satisfying timing constraints
 Chip area and timing constraints are inversely proportional to each other
 Layout design with timing constraints is called timing-driven layout
 Partitioning involves dividing the network such that the interconnections in
between the divided parts are minimized
 Simultaneous development of structure and layout is floorplanning

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Layout Design (2)

 Through floorplanning layout information becomes available at early design

stages; necessary changes can be made immediately
 For full-custom chips, designers appreciate freedom of editing layout
directly
 Layout editors are available for editing layer by layer in the final layout
 In addition to the convenience, it is a good source of errors
 When technology changes, the layout has to be changed
 Scaling down does not work
 Symbolic layout is used to address this problem
 The positions and patterns in symbolic layout are described relative to each
other forming the topology of the design
 This has to be used in conjunction with a compactor

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Layout Editor: Example

 Custom Compiler Layout Assistants

(Synopsys)
 Virtuoso Layout Suite (Cadence)
 Pyxis Layout (Mentor Graphics)

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Verification

 Verification executed in 3 ways

 Prototyping
 Build the system on a bread-board to test. This is called bread-boarding
 Not feasible for large designs
 ASICs can also be verified by using programmable devices such as FPGAs. This is called rapid system
prototyping
 Simulation
 Making a computer model for all modules
 Performing system level simulation
 Observing output signals to verify
 Testing cannot be exhaustive; only certain input patterns are checked
 Test vectors, test pattern generation
 Formal Verification
 The algorithm that the chip implements is re-constructed from gate level netlists
 The Boolean expressions are verified to ensure correctness
 No need of test vector

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Verification problem
Simulation Cycle Based

Event Driven
 Today about 70% of design Formal
Verification
cost and effort is spent on Functional Code
verification. Verification Coverage
 Verification teams are often Assertion
Based
almost twice as large as the Emulation
RTL designers at companies Analog Mixed
Signal
developing ICs. Simulation
Verification/ Timing
 Traditionally, chip design Validation Verification
verification focuses on
simulation. Testing
(DFT)
 However, new verification
techniques are emerging Physical
Verification
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Design Management Tools

 EDA tools consume and produce design data in different design

domains and at different levels of abstraction
 Data has to be stored in databases
 Amount of data is enormous and appropriate for data management
techniques
 Version management is also required to backtrack and undo certain
design steps and decisions
 Tools integration efforts require standards. This gave raise to the
EDIF format; though not very successful
 Utopia: Automate all the way up to cost management; however it is
far away from realistic implementation

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